- Launch the Xilinx System
Debugger by selecting .
- In the AMD command shell
window, change to the Example Design Project directory:
Vivado% cd ./<IP instance name>_ex
- Invoke Xilinx System Debugger (xsdb).
Vivado% xsdb
- Establish connections to debug targets.
xsdb% connect
- List all available JTAG targets.
xsdb% targets
1 PS TAP
2 PMU
3 PL
4 PSU
5 RPU (Reset)
6 Cortex-R5 #0 (RPU Reset)
7 Cortex-R5 #1 (RPU Reset)
8 APU
9* Cortex-A53 #0 (Running)
10 Cortex-A53 #1 (Power On Reset)
11 Cortex-A53 #2 (Power On Reset)
12 Cortex-A53 #3 (Power On Reset)
Note: The target
number for PSU, PL, APU and
Cortex®-A53 might
be different. Run the targets and ensure they are using the correct target number.
- Download the bitstream to the
PL.
xsdb% target -set 3 (PL)
xsdb% fpga -file ./<IP instance name>_ex.runs/impl_1/exdes_wrapper.bit
xsdd% after 2000
- Set the target processor.
xsdb% target -set 9 (Cortex-A53 #0)
xsdb% rst -processor
xsdb% dow ./<vitis_workspace>/<platform_name>/export/<platform_name>/sw/<platform_name>/boot/fsbl.elf
xsdb% after 1000
xsdb% con
xsdb% after 1000
xsdb% stop
xsdb% after 1000
- Download the software .elf to
the
PS.
xsdb% dow ./<vitis_workspace>/<application_name>_1/Debug/<application_name>_1.elf
- Run the software.
xsdb% con
- Exit the XSDB command prompt.
xsdb% exit