- Ensure that all the timing constraints and all other constraints were met during implementation.
- Ensure that all clock sources are active and clean.
- If using MMCMs in the design, ensure that all MMCMs have obtained lock by monitoring the
locked port.
- If your outputs go to 0, check your licensing.
- User LEDs
(ZCU102/ZCU106/VCU118/VCK190/VEK280)
- LED0 - HDMI 2.1 TX Subsystem
lock (when the HDMI Example Design is used)
- Use the debug port
to check if there are link data driven to the HDMI PHY Controller
/HDMI GT Subsystem
core.
- See the Debugging
Appendix in the
HDMI PHY Controller LogiCORE IP Product Guide
(PG333)
/
HDMI GT Controller LogiCORE IP Product Guide
(PG334)
, and ensure there is no problem with
clocking issues.