Clock frequency constraints are
required for the s_axi_cpu_aclk, s_axis_video_aclk, s_axis_audio_aclk, m_hdr_axi_clk, link_clk, frl_clk, and
video_clk.
create_clock -name s_axi_cpu_aclk -period 10.0 [get_ports s_axi_cpu_aclk]
create_clock -name s_axis_audio_aclk -period 10.0 [get_ports s_axis_audio_aclk]
create_clock -name video_clk -period 2.5 [get_ports video_clk]
create_clock -name s_axis_video_aclk -period 2.5 [get_ports s_axis_video_aclk]
create_clock -name link_clk -period 3.333 [get_ports link_clk]
create_clock -name frl_clk -period 2.222 [get_ports frl_clk]
create_clock -name m_hdr_axi_clk-period 3.333 [get_ports m_hdr_axi_clk]When using this subsystem in the
Vivado Design Suite flow with HDMI PHY Controller
/HDMI GT Subsystem modules, link_clk, and video_clk are generated
from the HDMI PHY Controller
/HDMI GT Subsystem. Therefore, the clock constraints are
set to the HDMI PHY Controller
/HDMI GT Subsystem constraints instead of these generated
clocks. See Clocking in the
HDMI PHY Controller LogiCORE IP Product Guide
(PG333)
/
HDMI GT Controller LogiCORE IP Product Guide
(PG334)
for
more information.
The frl_clk, s_axi_cpu_aclk, s_axis_video_aclk, s_axis_audio_aclk, and m_hdr_axi_clk
constraints are generated at system level, for example by using a clock wizard.