Miscellaneous Signals - 1.2 English

HDMI 2.1 Transmitter Subsystem v1.2 Product Guide (PG350)

Document ID
Release Date
1.2 English

The following table shows the miscellaneous signals.

Table 1. Miscellaneous Signals
Name I/O Width Description
hpd I 1

If XGUI option: Hot Plug Detect active-High (Default)

  • 0 - Hot Plug Detect is released
  • 1 - Hot Plug Detect is asserted

If XGUI option: Hot Plug Detect active-Low 1

  • 0 - Hot Plug Detect is asserted
  • 1 - Hot Plug Detect is released
locked 2 O 1

Flag indicating the AXI4-Stream to Video Out Bridge in the subsystem is locked to the incoming video stream.

  • 0 - no lock
  • 1 - locked
irq O 1 Interrupt request for CPU. Active-High.
frl_clk I 1 Fixed FRL link clock.
video_clk I 1

Reference Native Video Clock

When AXI4-Stream is selected as Video Interface, an AXI4-Stream to Video Out Bridge module is added to the HDMI 2.1 TX Subsystem to convert AXI4-Stream Video into Native Video. The HDMI TX core uses this video_clk to clock in the Video Data together with the video_cke_in.

video_cke_in I 1

Video clock enable signal

FRL Mode: video_cke_in is used to synchronize the video data rate of the HDMI TX core with the HDMI RX core in cases where a frame buffer is not used. This port is not intended to be used with systems using a frame buffer or data source other than the HDMI RX Core. HDMI RX Core video_cke_out should be connected to video_cke_in. Make sure video_cke_out from the HDMI RX core is synchronized to the HDMI TX clock domain; see the passthrough example design for an example on how this is implemented.

TMDS Mode: Not used

Tie to 1 if not used.

SB_STATUS_IN_tdata I 8

Side Band Status input signals

  • Bit 0: link_rdy
  • Bit 1: video_rdy
  • Bits [7:2]: Reserved
SB_STATUS_IN_tvalid I 1 Side Band Status input valid
fid 2 I 1

Field ID for AXI4-Stream bus. Used only for interlaced video.

  • 0 - even field
  • 1 - odd field

This bit is sampled coincident with the SOF on the AXI4-Stream bus. If the signal is not used, set the input to Low.

video_rst 3 O 1 Video reset signal in video_clk domain. Active-High.
video_cke_out 3 O 1 Clock Enable for Video Clock. Active-High.
  1. The Hot Plug Detect (HPD) signal is driven by an HDMI sink and asserted when the HDMI cable is connected to notify the HDMI source of the presence of an HDMI sink. In some cases, the HDMI sink is simply connected to 5V power signal. Therefore, in the PCB, if you choose to use a voltage divider or level shifter, the HPD polarity remains as active-High. However, if you add an inverter to the HPD signal, then the HPD polarity must be set to active-Low in the HDMI 2.1 TX Subsystem GUI.
  2. Applicable only for when the AXI4-Stream video interface present.
  3. Applicable only for when the Native Video or Native Video (Vectored DE) interface present.