Audio Clock Regeneration Interface - 1.2 English

HDMI 2.1 Transmitter Subsystem v1.2 Product Guide (PG350)

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1.2 English

The HDMI 2.1 TX Subsystem has internal logic to generate Audio Clock Regeneration (ACR) packets. At the same time, it offers the option to take in an ACR Cycle Time Stamp (CTS) parameter vector and Audio Clock Regeneration Value (N) parameter vector through the ACR input interface. Both vectors are 20 bits wide. The valid signal is driven High when the CTS and N parameters are stable. For more information, see Chapter 9 of the HDMI 2.1 specification.

On the rising edge of the valid signal, the TX reads the CTS and N parameters from the ACR input interface and transmits an audio clock regeneration packet.

The following table shows the Audio Clock Regeneration (ACR) interface signals. This interface runs at the s_axis_audio_aclk clock rate.

Table 1. Audio Clock Regeneration (ACR) Interface
Name I/O Width Description
acr_cts I 20 CTS
acr_n I 20 N
acr_valid I 1 Valid

When internal ACR generation is selected, leave the external ACR input pins open or connect them to fixed values, for example, tie the following inputs ports Low:

  • acr_cts
  • acr_n
  • acr_valid

If an HDMI system does not require audio, tie the following input ports Low:

  • AUDIO_IN (except tready)
  • s_axis_audio_aresetn
  • s_axis_audio_aclk
  • acr_cts
  • acr_n
  • acr_valid

However, the audio clock regeneration itself is not part of the HDMI 2.1 TX Subsystem. You must provide an audio clock to the application. This can be from an internal PLL or external clock source, depending on the audio clock requirements, audio sample frequency, and jitter.