The HDMI 2.1 TX Subsystem converts video and audio streams into an HDMI stream based on the selected video format set by the processor through the CPU interface. The subsystem then transmits the HDMI stream to the PHY Layer (HDMI PHY Controller /HDMI GT Subsystem) which converts the data into electronic signals, then sent to an HDMI sink through an HDMI cable.
The HDMI 2.1 TX Subsystem supports both Transition Minimized Differential Signaling (TMDS) and Fixed Rate Link (FRL) protocol based on the capability of the connected HDMI sink. As shown in the following figure, the HDMI 2.1 Transmitter subcore contains two separate data paths. One encodes the video stream into TMDS signal, and the other packetizes the video stream into FRL packets, adding FEC parity and encode it according to the 16b/18b coding mechanism in the HDMI 2.1 specification. A data multiplexer selects TMDS or FRL sending to the PHY layer. The HDMI PHY Controller /HDMI GT Subsystem controls the PHY layer, capable of supporting both TMDS and FRL (at rates up to 12 Gb/s).