The CPU interface is an AXI4-Lite bus interface, which is connected to a processor (Zynq UltraScale+ MPSoC processor or MicroBlaze™ ™). Multiple sub-modules are used to construct the HDMI 2.1 TX Subsystem and all the sub-modules which require software access are connected through an AXI crossbar. Therefore, the processor can access and control each individual sub-module inside the HDMI 2.1 TX Subsystem.
The following table shows the AXI4-Lite control interface signals. This interface is an AXI4-Lite interface and runs at the s_axi_cpu_aclk clock rate. Control of the subsystem is
only supported through the subsystem driver.
| Name | I/O | Width | Description |
|---|---|---|---|
| s_axi_cpu_aresetn | I | 1 | Reset (Active-Low) |
| s_axi_cpu_aclk | I | 1 | Clock for AXI4-Lite control interface |
| S_AXI_CPU_IN_awaddr | I | 17 or 19 | Write address |
| S_AXI_CPU_IN_awprot | I | 3 | Write address protection |
| S_AXI_CPU_IN_awvalid | I | 1 | Write address valid |
| S_AXI_CPU_IN_awready | O | 1 | Write address ready |
| S_AXI_CPU_IN_wdata | I | 32 | Write data |
| S_AXI_CPU_IN_wstrb | I | 4 | Write data strobe |
| S_AXI_CPU_IN_wvalid | I | 1 | Write data valid |
| S_AXI_CPU_IN_wready | O | 1 | Write data ready |
| S_AXI_CPU_IN_bresp | O | 2 | Write response |
| S_AXI_CPU_IN_bvalid | O | 1 | Write response valid |
| S_AXI_CPU_IN_bready | I | 1 | Write response ready |
| S_AXI_CPU_IN_araddr | I | 17 or 19 | Read address |
| S_AXI_CPU_IN_arprot | I | 3 | Read address protection |
| S_AXI_CPU_IN_arvalid | I | 1 | Read address valid |
| S_AXI_CPU_IN_aready | O | 1 | Read address ready |
| S_AXI_CPU_IN_rdata | O | 32 | Read data |
| S_AXI_CPU_IN_rresp | O | 2 | Read data response |
| S_AXI_CPU_IN_rvalid | O | 1 | Read data valid |
| S_AXI_CPU_IN_rready | I | 1 | Read data ready |
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