Dynamic HDR Interface (Memory Mapped AXI4 Interface) - 1.2 English

HDMI 2.1 Transmitter Subsystem v1.2 Product Guide (PG350)
Document ID
PG350
Release Date
2023-10-18
Version
1.2 English

The following table shows the M_HDR_AXI interface signals. This interface is a memory mapped AXI4 interface and runs at the m_hdr_axi_aclk clock rate. The memory mapped Dynamic HDR interface is only present when you select Enable Dynamic HDR Support in the IDE.

For more information on the memory mapped AXI4 interface, refer to the Vivado Design Suite: AXI Reference Guide (UG1037).

Table 1. Dynamic HDR Memory Mapped AXI4 Interface
Name I/O Width Description
m_hdr_axi_aresetn I 1 Reset (Active-Low)
m_hdr_axi_aclk I 1 Clock for M_HDR_AXI interface.
M_HDR_AXI_* AXI4-M Address and data width are 64 See the Vivado Design Suite: AXI Reference Guide (UG1037) for the description of the AXI4 signals.