Prerequisites - 2.5 English

Video Frame Buffer Read and Video Frame Buffer Write LogiCORE IP Product Guide (PG278)

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2.5 English

There are certain requirements that must be fulfilled when programming the core.

  • The core does not contain a data realignment engine; therefore, the application software must align the memory address before writing to the register. The alignment requirement is specified below. This ensures the start address is aligned with the width of the memory interface.
    Note: The start address should be aligned with: (8 * Pixels per Clock) Bytes.
  • The Stride value (in bytes) must be aligned as above to make sure that every row of pixels starts at an aligned memory location. To compute the stride from the width in pixels, the following equation can be used:
    Stride in Bytes ≥ (Width × Bytes per Pixel);

    The bytes per pixel value varies per video in memory format, and is described in Memory Mapped AXI4 Interface.

    Note: Padding bytes is sometimes necessary (hence, the ≥ in the equation) to make sure that every row of pixels starts at an address that is aligned with the size of the data on the memory mapped interface.
  • The Width value must be a multiple of Pixels per Clock as selected in the Vivado IDE for this core.