General Design Guidelines - 3.0 English - PG278

This section compares the differences between Video Frame Buffer Read and Video Frame Buffer Write IPs to the AXI Video Direct Memory Access IP core.

The AXI Video Direct Memory Access (VDMA) does not perform pixel packing or unpacking of data it reads and writes to and from memory. Data is written to memory as it is formatted on the AXIS_VIDEO_TDATA bus. This has the following consequences:

• 8-bit RGB is written to memory as GBR.
• YUV 4:2:2 over a three-component streaming interface is written to memory as three components although the third component does not contain any valid data.
• YUV 4:2:0 is the same as YUV 4:2:2. This means 4:2:0 takes twice the bandwidth compared to separating out luma and chroma planes.
• 10-bit formats are written differently to memory depending on pixels per clock. For example, with one pixel per clock, RGBX is written as:

  31:30	29:20	19:10	9:0
  X	R	B	G

Whereas with two pixels per clock, RGBX is written as:

Video Frame Buffer Read and Video Frame Buffer Write IPs have some differences/limitations when compared to AXI VDMA. The following list highlights some key differences between Video Frame Buffer IP and AXI VDMA.

• Video Frame Buffer Read and Video Frame Buffer Write cores support single channel read or single channel write, but never combined. The AXI VDMA supports combined read and write channels in one IP.
• Because of the previous point, Video Frame Buffer Read and Video Frame Buffer Writecores do not use Genlock Synchronization (prevents reading and writing from and to one buffer). You should implement this in the software.
• Video Frame Buffer Read and Video Frame Buffer Write cores currently only support 8, 10, and 12 bits per component.
• Video Frame Buffer Read and Video Frame Buffer Write cores do not allow for data realignment to the byte (8 bits) level. For example, the addresses must be aligned to multiples of memory mapped data width bytes.
• Video Frame Buffer Read and Video Frame Buffer Write cores do not allow for explicit control of the size of the memory bus. If data width conversion is required, use an AXI interconnect IP.