The Video Frame Buffer Read and Video Frame Buffer Write IPs have only a hardware
reset option, ap_rst_n
pin. No software reset option is
available. The external reset pulse must be held for 16 or more ap_clk
cycles to reset the core. The ap_rst_n
signal is synchronous to the ap_clk
clock domain. The ap_rst_n
signal resets the entire core, including the AXI4-Lite, AXI4-Stream, and
memory mapped AXI4 interfaces.