The Video Frame Buffer Read and Video Frame Buffer
Write cores have
either an AXI4-Stream video input or output
interface named s_axis_video or m_axis_video, respectively. All video streaming
interfaces follow the interface specification as defined in the
AXI4-Stream Video IP and System Design Guide (UG934). The video AXI4-Stream interface can be single, dual, quad, or
octa pixels per clock and can support 8, 10, or 12-bit per component.
The following tables explain the pixel mapping of an AXI4-Stream interface with two pixels per clock and
10 bits per component configuration for all supported color formats. Given that the
Video Frame Buffer Read and Video Frame Buffer
Write always require a hardware
configuration of three component video, the AXI4-Stream Subset Converter is needed to hook up with other IPs of
two or one component video interface in YUV 4:2:2, YUV 4:2:0, or Luma-Only.
Table 1. Dual Pixels per Clock, 10 Bits per Component Mapping for
RGB
| 63:60 |
59:50 |
49:40 |
39:30 |
29:20 |
19:10 |
9:0 |
| zero padding |
R1 |
B1 |
G1 |
R0 |
B0 |
G0 |
Table 2. Dual Pixels per Clock, 10 Bits per Component Mapping for YUV
4:4:4
| 63:60 |
59:50 |
49:40 |
39:30 |
29:20 |
19:10 |
9:0 |
| zero padding |
V1 |
U1 |
Y1 |
V0 |
U0 |
Y0 |
Table 3. Dual Pixels per Clock, 10 Bits per Component Mapping for YUV
4:2:2
| 63:60 |
59:50 |
49:40 |
39:30 |
29:20 |
19:10 |
9:0 |
| zero padding |
zero padding |
zero padding |
V0 |
Y1 |
U0 |
Y0 |
Table 4. Dual Pixels per Clock, 10 Bits per Component Mapping for YUV
4:2:0, for Even Lines
| 63:60 |
59:50 |
49:40 |
39:30 |
29:20 |
19:10 |
9:0 |
| zero padding |
zero padding |
zero padding |
V0 |
Y1 |
U0 |
Y0 |
Table 5. Dual Pixels per Clock, 10 Bits per Component Mapping for YUV
4:2:0, for Odd Lines
| 63:60 |
59:50 |
49:40 |
39:30 |
29:20 |
19:10 |
9:0 |
| zero padding |
zero padding |
zero padding |
zero padding |
Y1 |
zero padding |
Y0 |
This IP always generates three video components even if the video
format is set to be YUV 4:2:0 or YUV 4:2:2 at runtime. The unused components can be
set to zero.
The following table shows the interface signals for input and output
AXI4-Stream video streaming interfaces.
Table 6. AXI4-Stream Interface Signals
| Signal Name |
I/O |
Width |
Description |
| s_axis_tdata |
I |
floor(((number_of_components × bits_per_component
× pixels_per_clock) + 7) / 8) × 8 |
Input Data |
| s_axis_tready |
O |
1 |
Input Ready |
| s_axis_tvalid |
O |
1 |
Input Valid |
| s_axis_tdest |
I |
1 |
Input Data Routing Identifier |
| s_axis_tkeep |
I |
(s_axis_video_tdata width) / 8 |
Input byte qualifier that indicates whether the
content of the associated byte of TDATA is processed as part of the
data stream. |
| s_axis_tlast |
I |
1 |
Input End of Line |
| s_axis_tstrb |
I |
(s_axis_video_tdata width) / 8 |
Input byte qualifier that indicates whether the
content of the associated byte of TDATA is processed as a data byte
or a position byte. |
| s_axis_tuser |
I |
1 |
Input Start of Frame |
| m_axis_tdata |
O |
floor(((number_of_components ×
bits_per_component × pixels_per_clock) + 7) / 8) × 8 |
Output Data |
| m_axis_tdest |
O |
1 |
Output Data Routing Identifier |
| m_axis_tid |
O |
1 |
Output Data Stream Identifier |
| m_axis_tkeep |
O |
(m_axis_video_tdata width) / 8 |
Output byte qualifier that indicates whether the
content of the associated byte of TDATA is processed as part of the
data stream. |
| m_axis_tlast |
O |
1 |
Output End of Line |
| m_axis_tready |
I |
1 |
Output Ready |
| m_axis_tstrb |
O |
(m_axis_video_tdata width) / 8 |
Output byte qualifier that indicates whether the
content of the associated byte of TDATA is processed as a data byte
or a position byte. |
| m_axis_tuser |
O |
1 |
Output Start of Frame |
| m_axis_tvalid |
O |
1 |
Output Valid |
All video streaming interfaces run at the IP core clock speed, that
is, ap_clk.