Frame Buffer Read Example Design - 2.5 English

The example design delivered with the Frame Buffer Read IP contains the following video IP cores: Video Frame Buffer Read, Video Timing Controller, and AXI4-Stream to Video Output bridge. The design also contains a processor (to enable register programming) connected to an AXI Interconnect. A Memory Interface Generator (MIG) is used for DDR memory access.

The processor acts as the system's AXI master and drives the Video Frame Buffer Read and Video Timing Controller cores. It configures the height, width, and other registers of the Video Frame Buffer Read. It then configures the timing parameters of the Video Timing Controller core.

The Video Frame Buffer Read core generates video stream pixels at a clock rate of ap_clk. The core reads frames from a memory mapped AXI4 memory interface and sends the data out over the AXI4-Stream master interface.

The AXI4-Stream to Video Out core, working with the Video Timing Controller, interfaces with the AXI4-Stream interface implementing a timed Video Protocol to a video source (parallel video data with video syncs and blanks).

The example design checks the LOCKED output from the AXI4-Stream to the Video Out core. A locked port indicates that the output timing is locked to the output video. The example design indicates that the test is completed successfully if the video lock is successfully detected. The locked port of AXI4-Stream to Video Out is connected to the AXI GPIO core and the processor polls the corresponding register for a sign that the test passed.