Programming Sequence - 2.5 English

Video Frame Buffer Read and Video Frame Buffer Write LogiCORE IP Product Guide (PG278)

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2.5 English

The Buffer parameters of the IP can be changed dynamically and the change is picked up immediately. If the Width, Height, Stride, or Video Format must be changed or the entire system restarted, it is recommended that pipelined AMD IP video cores are disabled/reset from system output towards the system input, and programmed/enabled from system output to system input.

Pending AXI transactions can be flushed before resetting the IP. Assert and hold Bit[5] of the Control register. Bit[6] asserts when the flush is complete and then the IP can be reset.

For interlaced video, with the ap_ready interrupt, the current Field ID can be read for the Video Frame Buffer Write IP, and the next Field ID can be programmed for the Frame Buffer Read IP.