The following settings are generally applicable:
- Component Name
- The component name is used as the base name of output files generated for the module. Names must begin with a letter and must be composed of characters: a to z, 0 to 9, and "_".
- Samples Per Clock
- Specifies the number of pixels processed per clock cycle. Permitted values are one, two, four, and eight samples per clock. This parameter determines the IP throughput. The more samples per clock, the larger throughput it provides. The larger throughput always needs more hardware resources.
- Maximum Number of Columns
- Specifies maximum active video columns/pixels the IP core could produce at runtime. Any video width that is less than the Maximum Number of Columns can be programmed through the AXI4-Lite control interface without regenerating the core.
- Maximum Number of Rows
- Specifies maximum active video rows/lines the IP core could produce at runtime. Any video height that is less than Maximum Number of Rows can be programmed through the AXI4-Lite control interface without regenerating the core.
- Maximum Data Width
- Specifies the bit width of input and output samples on all the streaming interfaces. Permitted values are 8, 10, and 12 bits. This parameter should match the Video Component Width of the video IP core connected to the AXI4-Stream video interface.
- Memory Video Format
- Specifies the order in which the pixel component data is written into or read from memory. Available formats are raster order and tile order.
- Address Width
- Specifies the address width of the AXI master interfaces for the memory interface, either 32 or 64 bits.
- Interlaced Support
- Select for support of interlaced video (in addition to progressive video).
- Video Formats
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Both packed and semi-planar formats are offered. If only packed formats are selected, the IP is smaller in size because there is only one plane. The following formats are packed and only need one plane:
- RGBX8
- BGRX8
- YUVX8
- YUYV8
- UYVY8
- RGBA8
- BGRA8
- YUVA8
- RGBX10
- YUVX10
- RGB8
- BGR8
- YUV8
- Y8
- Y10
- Y12
The following formats are semi-planar and require two planes:
- Y_UV8
- Y_UV8_420
- Y_UV10
- Y_UV10_410
- Y_UV12
- Y_UV12_410
The following formats are 3 planar and require three planes:
- Y_U_V8
- Y_U_V8_420
- Y_U_V10
- Y_U_V12
Note: Tile mode memory format uses line buffers to store the pixel data on chip. The PL RAM usage of line buffers is proportional to the maximum data width, sample per clock, maximum height and maximum width settings. To reduce the PL RAM usage, it is suggested to set these parameters as per your requirements.Select the memory video formats to be supported. The video format can be programmed through the AXI4-Lite control interface. Details on each video format can be found in the Memory Mapped AXI4 Interface.