The Plane 1 Buffer register specifies the frame buffer address of plane 1. Note that for the semi-planar formats (Y_UV8, Y_UV8_20, Y_UV10, Y_UV10_420), the chroma buffer is specified by the Plane 2 Buffer register, and for 3 planar formats (Y_U_V8 , Y_U_V10, and Y_U_V8_420), the chroma buffers are specified by the Plane 2 and Plane 3 Buffer registers. The address needs to be aligned with the data size of the memory mapped AXI4 interface. The data size of the memory mapped AXI4 interface is 64*Samples per Clock bits, for example- 64, 128, 256, or 512 bits for one, two, four, and eight samples per clock, respectively.
If the IP is configured to a 64-bit address width in the IP catalog, the IP internally creates another register in the register space by adding 0x4 to the existing buffer address register offset. For example, Plane1 Buffer register addresses are 0x0030 and 0x0034.