Revision History - 2.5 English

Video Frame Buffer Read and Video Frame Buffer Write LogiCORE IP Product Guide (PG278)

Document ID
Release Date
2.5 English

The following table shows the revision history for this document.

Section Revision Summary
11/19/2023 Version 2.5
Entire Document Added Y_U_V8_420 and Y_U_V8 video formats where applicable
04/12/2023 Version 2.4
IP Facts Updated the PRU links.
05/11/2022 Version 2.4
Product Specification Added Y_U_V10.
User Parameters Updated the table.
Upgrading in the Vivado Design Suite Updated the section.
10/27/2021 Version 2.3
  • Added support for 16K resolution and 3 Planar video format
  • Updated enhancement for field ID signal
Example Design Added support for AMD Versalâ„¢ example design.
02/04/2021 Version 2.2
Vitis Software Platform Workflow Updated for v2.2.
07/08/2020 Version 2.1
  • Updated AXI-Stream Video Interface section in Chapter 2.
  • Updated Control (0x0000) Register in Chapter 2.
  • Updated Stride (0x0020) Register in Chapter 2.
  • Updated Plane1 Buffer (0x0030) and Plane 2 Buffer (0x003C) Registers in Chapter 2.
  • Updated Samples Per Clock description in Chapter 4.
12/19/2019 Version 2.1
Design Flow Steps Vitis flow updated.
11/14/2018 Version 2.1
Features Added support for 8K30.
fid error Updated the UG934 link.
Memory Mapped AXI4 Interface Added Table 2.
Table 2 Updated UG934 link in Note.
N/A Fixed AR 68764 link.
04/04/2018 Version 2.0
  • Added support for interlaced video
  • Added BGR8 video format
  • Added support for ZCU102, ZCU104, and ZCU106 boards in the example design.
10/04/2017 Version 2.0
N/A Added new video formats, added second buffer for semi-planar formats, added support for 64-bit addressing on memory interfaces.
04/05/2017 Version 1.0
N/A Initial AMD release.