|
Core Specifics |
| Supported Device Family
1
|
AMD Versal™
Adaptive SoC,
AMD UltraScale+™
Families, AMD UltraScale™
Families, AMD Zynq™ 7000 SoC, 7 series
|
| Supported User Interfaces |
AXI4-Master, AXI4-Lite, AXI4-Stream
2
|
| Resources |
- Read
-
Performance and Resource Utilization for
Video Frame Buffer Read web page
- Write
-
Performance and Resource Utilization for
Video Frame Buffer Write web page
|
| Provided with
Core
|
| Design Files |
Not Provided |
| Example Design |
Yes |
| Test Bench |
Not Provided |
| Constraints File |
Xilinx Design Constraints (XDC) |
| Simulation Model |
Encrypted RTL |
| Supported S/W Driver
3
|
Standalone Linux DMA Controller |
| Tested Design
Flows
4
|
| Design Entry |
AMD Vivado™ Design Suite
|
| Simulation |
For supported simulators, see the Vitis Software Platform Release
Notes. |
| Synthesis |
VivadoSynthesis |
| Support |
| Release Notes and Known Issues |
Master Answer Record
- Read
-
68764
- Write
-
68765
|
| All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775
|
| Support web
page |
- For a complete list of supported devices, see the AMD Vivado™
IP catalog.
-
Video protocol as defined in the Video IP: AXI Feature Adoption section of
Vivado Design Suite: AXI Reference
Guide (UG1037).
- Linux OS and driver support information is available from the
Linux Video Frame Buffer Read Driver Page
and Linux Video Frame Buffer Write Driver
Page.
- For the supported versions of third-party
tools, see the Vitis Software Platform Release
Notes.
|