The stride determines the number of bytes between rows of pixels in memory. When a video frame is stored in memory, the memory buffer might contain extra padding bytes after each row of pixels. The padding bytes only affect how the image is stored in memory but do not affect how the image is displayed.
Padding bytes are necessary to ensure that every row of pixels starts at an address that is aligned with the size of the data on the memory mapped AXI4 interface. The stride value needs to be calculated based on order of pixel components in memory. The stride value must be a multiple of the memory-mapped AXI4 data size. The data size of the memory mapped AXI4 interface is 64*Samples per Clock bits, for example, 64, 128, 256, or 512 bits for one, two, four, and eight samples per clock, respectively.
- Memory in Tile Order
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The stride value in tile order defines the address offset between two consecutive rows of tiles. A row of tiles corresponds to four pixel rows. The stride value must be a multiple of 32 byte. The default value of the stride (in bytes) used by the control software for tile size of n × 4 (where n = 32 or 64) is:
(((PictureWidth + (n-1) & ~(n-1)) * 4 * bit-depth) / 8