XADC Specifications

V_CCADC = 1.8V ± 5%, V_REFP = 1.25V, V_REFN = 0V, ADCCLK = 26 MHz, –55°C £ T_j £ 125°C.
Typical values at T_j = +40°C.

ADC Accuracy⁽¹⁾

Resolution

12

–

–

Bits

Integral nonlinearity⁽²⁾

INL

–40°C £ T_j £ 100°C

–

–

±2

LSBs

–55°C £ T_j < –40°C; 100°C < T_j £ 125°C

–

–

±3

LSBs

Differential nonlinearity

DNL

No missing codes, guaranteed monotonic.

–

–

±1

LSBs

Offset error

Unipolar

–40°C £ T_j £ 100°C

–

–

±8

LSBs

–55°C £ T_j < –40°C; 100°C < T_j £ 125°C

–

–

±12

LSBs

Bipolar

–55°C £ T_j £ 125°C

–

–

±4

LSBs

Gain error

–

–

±0.5

%

Offset matching

–

–

4

LSBs

Gain matching

–

–

0.3

%

Sample rate

–

–

1

MS/s

Signal to noise ratio⁽²⁾

SNR

F_SAMPLE = 500 KS/s, F_IN = 20 kHz

60

–

–

dB

RMS code noise

External 1.25V reference.

–

–

2

LSBs

On-chip reference.

–

3

–

LSBs

Total harmonic distortion⁽²⁾

THD

F_SAMPLE = 500 KS/s, F_IN = 20 kHz

70

–

–

dB

Analog Inputs⁽³⁾

ADC input ranges

Unipolar operation.

0

–

1

V

Bipolar operation.

–0.5

–

+0.5

V

Unipolar common mode range (FS input).

0

–

+0.5

V

Bipolar common mode range (FS input).

+0.5

–

+0.6

V

Maximum external channel input ranges

Adjacent analog channels set within these ranges should not corrupt measurements on adjacent channels.

–0.1

–

V_CCADC

V

Full-resolution bandwidth

FRBW

Auxiliary channel full resolution bandwidth.

250

–

–

kHz

On-chip Sensors

Temperature sensor error

–40°C £ T_j £ 100°C

–

–

±4

°C

–55°C £ T_j < –40°C; 100°C < T_j £ 125°C

–

–

±6

°C

Supply sensor error

–40°C £ T_j £ 100°C

–

–

±1

%

–55°C £ T_j < –40°C; 100°C < T_j £ 125°C

–

–

±2

%

Conversion Rate⁽⁴⁾

Conversion time: continuous

t_CONV

Number of ADCCLK cycles.

26

–

32

Cycles

Conversion time: event

t_CONV

Number of CLK cycles.

–

–

21

Cycles

DRP clock frequency

DCLK

DRP clock frequency.

8

–

250

MHz

ADC clock frequency

ADCCLK

Derived from DCLK.

1

–

26

MHz

DCLK duty cycle

40

–

60

%

XADC Reference⁽⁵⁾

External reference

V_REFP

Externally supplied reference voltage.

1.20

1.25

1.30

V

On-chip reference

Ground V_REFP pin to AGND,
–40°C £ T_j £ 100°C

1.2375

1.25

1.2625

V

Ground VREFP pin to AGND,
–55°C £ T_j < –40°C; 100°C < T_j £ 125°C

1.225

1.25

1.275

V

Notes:

1.Offset and gain errors are removed by enabling the XADC automatic gain calibration feature. The values are specified for when this feature is enabled.

2.Only specified for bitstream option XADCEnhancedLinearity = ON.

3.For a detailed description, see the ADC chapter in the 7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide (UG480) [Ref 9].

4.For a detailed description, see the Timing chapter in the 7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide (UG480) [Ref 9].

5.Any variation in the reference voltage from the nominal V_REFP = 1.25V and V_REFN = 0V will result in a deviation from the ideal transfer function. This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external ratiometric type applications allowing reference to vary by ±4% is permitted.