Block RAM and FIFO Switching Characteristics

Block RAM and FIFO Clock-to-Out Delays

T_{RCKO_DO} and T_{RCKO_DO_REG}

Clock CLK to DOUT output (without output register).⁽¹⁾⁽²⁾

2.13

2.46

2.46

ns, Max

Clock CLK to DOUT output (with output register).⁽³⁾⁽⁴⁾

0.74

0.89

0.89

ns, Max

T_{RCKO_DO_ECC} and T_{RCKO_DO_ECC_REG}

Clock CLK to DOUT output with ECC (without output register).⁽¹⁾⁽²⁾

3.04

3.84

3.84

ns, Max

Clock CLK to DOUT output with ECC (with output register).⁽³⁾⁽⁴⁾

0.81

0.94

0.94

ns, Max

T_{RCKO_DO_CASCOUT} and T_{RCKO_DO_CASCOUT_REG}

Clock CLK to DOUT output with cascade (without output register).⁽¹⁾

2.88

3.30

3.30

ns, Max

Clock CLK to DOUT output with cascade (with output register).⁽³⁾

1.28

1.46

1.46

ns, Max

T_{RCKO_FLAGS}

Clock CLK to FIFO flags outputs.⁽⁵⁾

0.87

1.05

1.05

ns, Max

T_{RCKO_POINTERS}

Clock CLK to FIFO pointers outputs.⁽⁶⁾

1.02

1.15

1.15

ns, Max

T_{RCKO_PARITY_ECC}

Clock CLK to ECCPARITY in ECC encode only mode.

0.85

0.94

0.94

ns, Max

T_{RCKO_SDBIT_ECC} and T_{RCKO_SDBIT_ECC_REG}

Clock CLK to BITERR (without output register).

2.81

3.55

3.55

ns, Max

Clock CLK to BITERR (with output register).

0.76

0.89

0.89

ns, Max

T_{RCKO_RDADDR_ECC} and T_{RCKO_RDADDR_ECC_REG}

Clock CLK to RDADDR output with ECC (without output register).

0.88

1.07

1.07

ns, Max

Clock CLK to RDADDR output with ECC (with output register).

0.93

1.08

1.08

ns, Max

Setup and Hold Times Before/After Clock CLK

T_{RCCK_ADDRA}/ T_{RCKC_ADDRA}

ADDR inputs.⁽⁷⁾

0.49/0.33

0.57/0.36

0.57/0.36

ns, Min

T_{RDCK_DI_WF_NC}/ T_{RCKD_DI_WF_NC}

Data input setup/hold time when block RAM is configured in WRITE_FIRST or NO_CHANGE mode.⁽⁸⁾

0.65/0.63

0.74/0.67

0.74/0.67

ns, Min

T_{RDCK_DI_RF}/ T_{RCKD_DI_RF}

Data input setup/hold time when block RAM is configured in READ_FIRST mode.⁽⁸⁾

0.22/0.34

0.25/0.41

0.25/0.41

ns, Min

T_{RDCK_DI_ECC}/ T_{RCKD_DI_ECC}

DIN inputs with block RAM ECC in standard mode.⁽⁸⁾

0.55/0.46

0.63/0.50

0.63/0.50

ns, Min

T_{RDCK_DI_ECCW}/ T_{RCKD_DI_ECCW}

DIN inputs with block RAM ECC encode only.⁽⁸⁾

1.02/0.46

1.17/0.50

1.17/0.50

ns, Min

T_{RDCK_DI_ECC_FIFO}/ T_{RCKD_DI_ECC_FIFO}

DIN inputs with FIFO ECC in standard mode.⁽⁸⁾

1.15/0.59

1.32/0.64

1.32/0.64

ns, Min

T_{RCCK_INJECTBITERR}/ T_{RCKC_INJECTBITERR}

Inject single/double bit error in ECC mode.

0.64/0.37

0.74/0.40

0.74/0.40

ns, Min

T_{RCCK_EN}/T_{RCKC_EN}

Block RAM enable (EN) input.

0.39/0.21

0.45/0.23

0.45/0.23

ns, Min

T_{RCCK_REGCE}/ T_{RCKC_REGCE}

CE input of output register.

0.29/0.15

0.36/0.16

0.36/0.16

ns, Min

T_{RCCK_RSTREG}/ T_{RCKC_RSTREG}

Synchronous RSTREG input.

0.32/0.07

0.35/0.07

0.35/0.07

ns, Min

T_{RCCK_RSTRAM}/ T_{RCKC_RSTRAM}

Synchronous RSTRAM input.

0.34/0.43

0.36/0.46

0.36/0.46

ns, Min

T_{RCCK_WEA}/T_{RCKC_WEA}

Write enable (WE) input (block RAM only).

0.48/0.19

0.54/0.20

0.54/0.20

ns, Min

T_{RCCK_WREN}/ T_{RCKC_WREN}

WREN FIFO inputs.

0.46/0.35

0.47/0.43

0.47/0.43

ns, Min

T_{RCCK_RDEN}/ T_{RCKC_RDEN}

RDEN FIFO inputs.

0.43/0.35

0.43/0.43

0.43/0.43

ns, Min

Reset Delays

T_{RCO_FLAGS}

Reset RST to FIFO flags/pointers.⁽⁹⁾

0.98

1.10

1.10

ns, Max

T_{RREC_RST}/T_{RREM_RST}

FIFO reset recovery and removal timing.⁽¹⁰⁾

2.07/–0.81

2.37/–0.81

2.37/–0.81

ns, Max

Maximum Frequency

F_{MAX_BRAM_WF_NC}

Block RAM (write first and no change modes) when not in SDP RF mode.

460.83

388.20

388.20

MHz

F_{MAX_BRAM_RF_
PERFORMANCE}

Block RAM (read first, performance mode) when in SDP RF mode but no address overlap between port A and
port B.

460.83

388.20

388.20

MHz

F_{MAX_BRAM_RF_
DELAYED_WRITE}

Block RAM (read first, delayed write mode) when in SDP RF mode and there is possibility of overlap between port A and port B addresses.

404.53

339.67

339.67

MHz

F_{MAX_CAS_WF_NC}

Block RAM cascade (write first, no change mode) when cascade but not in RF mode.

418.59

345.78

345.78

MHz

F_{MAX_CAS_RF_
PERFORMANCE}

Block RAM cascade (read first, performance mode) when in cascade with RF mode and no possibility of address overlap/one port is disabled.

418.59

345.78

345.78

MHz

F_{MAX_CAS_RF_
DELAYED_WRITE}

When in cascade RF mode and there is a possibility of address overlap between port A and port B.

362.19

297.35

297.35

MHz

F_{MAX_FIFO}

FIFO in all modes without ECC.

460.83

388.20

388.20

MHz

F_{MAX_ECC}

Block RAM and FIFO in ECC configuration.

365.10

297.53

297.53

MHz

Notes:

1.T_{RCKO_DOR} includes T_{RCKO_DOW}, T_{RCKO_DOPR}, and T_{RCKO_DOPW} as well as the B port equivalent timing parameters.

2.These parameters also apply to synchronous FIFO with DO_REG = 0.

3.T_{RCKO_DO} includes T_{RCKO_DOP} as well as the B port equivalent timing parameters.

4.These parameters also apply to multi-rate (asynchronous) and synchronous FIFO with DO_REG = 1.

5.T_{RCKO_FLAGS} includes the following parameters: T_{RCKO_AEMPTY}, T_{RCKO_AFULL}, T_{RCKO_EMPTY}, T_{RCKO_FULL}, T_{RCKO_RDERR}, T_{RCKO_WRERR}.

6.T_{RCKO_POINTERS} includes both T_{RCKO_RDCOUNT} and T_{RCKO_WRCOUNT}.

7.The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted). Otherwise, block RAM data corruption is possible.

8.These parameters include both A and B inputs as well as the parity inputs of A and B.

9.T_{RCO_FLAGS} includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT.

10.RDEN and WREN must be held Low prior to and during reset. The FIFO reset must be asserted for at least five positive clock edges of the slowest clock (WRCLK or RDCLK).