Input/Output Logic Switching Characteristics

Spartan 7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS189)

Document ID
DS189
Release Date
2024-10-18
Revision
1.11 English

Table 21: ILOGIC Switching Characteristics

Symbol

Description

VCCINT Operating Voltage and Speed Grade

Units

1.0V

0.95V

-2

-1

-1L

Setup/Hold

TICE1CK/TICKCE1

CE1 pin setup/hold with respect to CLK.

0.54/0.02

0.76/0.02

0.76/0.02

ns

TISRCK/TICKSR

SR pin setup/hold with respect to CLK.

0.70/0.01

1.13/0.01

1.13/0.01

ns

TIDOCK/TIOCKD

D pin setup/hold with respect to CLK without delay.

0.01/0.29

0.01/0.33

0.01/0.33

ns

TIDOCKD/TIOCKDD

DDLY pin setup/hold with respect to CLK (using IDELAY).

0.02/0.29

0.02/0.33

0.02/0.33

ns

Combinatorial

TIDI

D pin to O pin propagation delay, no delay.

0.11

0.13

0.13

ns

TIDID

DDLY pin to O pin propagation delay (using IDELAY).

0.12

0.14

0.14

ns

Sequential Delays

TIDLO

D pin to Q1 pin using flip-flop as a latch without delay.

0.44

0.51

0.51

ns

TIDLOD

DDLY pin to Q1 pin using flip-flop as a latch (using IDELAY).

0.44

0.51

0.51

ns

TICKQ

CLK to Q outputs.

0.57

0.66

0.66

ns

TRQ_ILOGIC

SR pin to OQ/TQ out.

1.08

1.32

1.32

ns

TGSRQ_ILOGIC

Global set/reset to Q outputs.

7.60

10.51

10.51

ns

Set/Reset

TRPW_ILOGIC

Minimum pulse width, SR inputs.

0.72

0.72

0.72

ns, Min

Table 22: OLOGIC Switching Characteristics

Symbol

Description

VCCINT Operating Voltage and Speed Grade

Units

1.0V

0.95V

-2

-1

-1L

Setup/Hold

TODCK/TOCKD

D1/D2 pins setup/hold with respect to CLK.

0.71/–0.11

0.84/–0.11

0.84/–0.11

ns

TOOCECK/TOCKOCE

OCE pin setup/hold with respect to CLK.

0.34/0.58

0.51/0.58

0.51/0.58

ns

TOSRCK/TOCKSR

SR pin setup/hold with respect to CLK.

0.44/0.21

0.80/0.21

0.80/0.21

ns

TOTCK/TOCKT

T1/T2 pins setup/hold with respect to CLK.

0.73/–0.14

0.89/–0.14

0.89/–0.14

ns

TOTCECK/TOCKTCE

TCE pin setup/hold with respect to CLK.

0.34/0.01

0.51/0.01

0.51/0.01

ns

Combinatorial

TODQ

D1 to OQ out or T1 to TQ out.

0.96

1.16

1.16

ns

Sequential Delays

TOCKQ

CLK to OQ/TQ out.

0.49

0.56

0.56

ns

TRQ_OLOGIC

SR pin to OQ/TQ out.

0.80

0.95

0.95

ns

TGSRQ_OLOGIC

Global set/reset to Q outputs.

7.60

10.51

10.51

ns

Set/Reset

TRPW_OLOGIC

Minimum pulse width, SR inputs.

0.74

0.74

0.74

ns, Min