Input/Output Logic Switching Characteristics

Setup/Hold

T_ICE1CK/T_ICKCE1

CE1 pin setup/hold with respect to CLK.

0.54/0.02

0.76/0.02

0.76/0.02

ns

T_ISRCK/T_ICKSR

SR pin setup/hold with respect to CLK.

0.70/0.01

1.13/0.01

1.13/0.01

ns

T_IDOCK/T_IOCKD

D pin setup/hold with respect to CLK without delay.

0.01/0.29

0.01/0.33

0.01/0.33

ns

T_IDOCKD/T_IOCKDD

DDLY pin setup/hold with respect to CLK (using IDELAY).

0.02/0.29

0.02/0.33

0.02/0.33

ns

Combinatorial

T_IDI

D pin to O pin propagation delay, no delay.

0.11

0.13

0.13

ns

T_IDID

DDLY pin to O pin propagation delay (using IDELAY).

0.12

0.14

0.14

ns

Sequential Delays

T_IDLO

D pin to Q1 pin using flip-flop as a latch without delay.

0.44

0.51

0.51

ns

T_IDLOD

DDLY pin to Q1 pin using flip-flop as a latch (using IDELAY).

0.44

0.51

0.51

ns

T_ICKQ

CLK to Q outputs.

0.57

0.66

0.66

ns

T_{RQ_ILOGIC}

SR pin to OQ/TQ out.

1.08

1.32

1.32

ns

T_{GSRQ_ILOGIC}

Global set/reset to Q outputs.

7.60

10.51

10.51

ns

Set/Reset

T_{RPW_ILOGIC}

Minimum pulse width, SR inputs.

0.72

0.72

0.72

ns, Min

Setup/Hold

T_ODCK/T_OCKD

D1/D2 pins setup/hold with respect to CLK.

0.71/–0.11

0.84/–0.11

0.84/–0.11

ns

T_OOCECK/T_OCKOCE

OCE pin setup/hold with respect to CLK.

0.34/0.58

0.51/0.58

0.51/0.58

ns

T_OSRCK/T_OCKSR

SR pin setup/hold with respect to CLK.

0.44/0.21

0.80/0.21

0.80/0.21

ns

T_OTCK/T_OCKT

T1/T2 pins setup/hold with respect to CLK.

0.73/–0.14

0.89/–0.14

0.89/–0.14

ns

T_OTCECK/T_OCKTCE

TCE pin setup/hold with respect to CLK.

0.34/0.01

0.51/0.01

0.51/0.01

ns

Combinatorial

T_ODQ

D1 to OQ out or T1 to TQ out.

0.96

1.16

1.16

ns

Sequential Delays

T_OCKQ

CLK to OQ/TQ out.

0.49

0.56

0.56

ns

T_{RQ_OLOGIC}

SR pin to OQ/TQ out.

0.80

0.95

0.95

ns

T_{GSRQ_OLOGIC}

Global set/reset to Q outputs.

7.60

10.51

10.51

ns

Set/Reset

T_{RPW_OLOGIC}

Minimum pulse width, SR inputs.

0.74

0.74

0.74

ns, Min