Input/Output Delay Switching Characteristics

IDELAYCTRL

T_{DLYCCO_RDY}

Reset to ready for IDELAYCTRL.

3.67

3.67

3.67

µs

F_{IDELAYCTRL_REF}

Attribute REFCLK frequency = 200.00.⁽¹⁾

200.00

200.00

200.00

MHz

Attribute REFCLK frequency = 300.00.⁽¹⁾

300.00

300.00

300.00

MHz

Attribute REFCLK frequency = 400.00.⁽¹⁾

400.00

N/A

N/A

MHz

IDELAYCTRL_REF_PRECISION

REFCLK precision

±10

±10

±10

MHz

T_{IDELAYCTRL_RPW}

Minimum reset pulse width.

59.28

59.28

59.28

ns

IDELAY

T_{IDELAYRESOLUTION}

IDELAY chain delay resolution.

1/(32 x 2 x F_REF)

µs

T_{IDELAYPAT_JIT}

Pattern dependent period jitter in delay chain for clock pattern.⁽²⁾

0

0

0

ps
per tap

Pattern dependent period jitter in delay chain for random data pattern (PRBS 23).⁽³⁾

±5

±5

±5

ps
per tap

Pattern dependent period jitter in delay chain for random data pattern (PRBS 23).⁽⁴⁾

±9

±9

±9

ps
per tap

T_{IDELAY_CLK_MAX}

Maximum frequency of CLK input to IDELAY.

680.00

600.00

600.00

MHz

T_{IDCCK_CE} / T_{IDCKC_CE}

CE pin setup/hold with respect to C for IDELAY.

0.16/0.13

0.21/0.16

0.21/0.16

ns

T_{IDCCK_INC}/ T_{IDCKC_INC}

INC pin setup/hold with respect to C for IDELAY.

0.14/0.18

0.16/0.22

0.16/0.22

ns

T_{IDCCK_RST}/ T_{IDCKC_RST}

RST pin setup/hold with respect to C for IDELAY.

0.16/0.11

0.18/0.14

0.18/0.14

ns

T_{IDDO_IDATAIN}

Propagation delay through IDELAY.

Note 5

Note 5

Note 5

ps

Notes:

1.Average tap delay at 200 MHz = 78 ps, at 300 MHz = 52 ps, and at 400 MHz = 39 ps.

2.When HIGH_PERFORMANCE mode is set to TRUE or FALSE.

3.When HIGH_PERFORMANCE mode is set to TRUE.

4.When HIGH_PERFORMANCE mode is set to FALSE.

5.Delay depends on IDELAY tap setting. See the timing report for actual values.

IO_FIFO Clock to Out Delays

T_{OFFCKO_DO}

RDCLK to Q outputs.

0.60

0.68

0.68

ns

T_{CKO_FLAGS}

Clock to IO_FIFO flags.

0.61

0.77

0.77

ns

Setup/Hold

T_{CCK_D}/T_{CKC_D}

D inputs to WRCLK.

0.51/0.02

0.58/0.02

0.58/0.02

ns

T_{IFFCCK_WREN}/ T_{IFFCKC_WREN}

WREN to WRCLK.

0.47/–0.01

0.53/–0.01

0.53/–0.01

ns

T_{OFFCCK_RDEN}/ T_{OFFCKC_RDEN}

RDEN to RDCLK.

0.58/0.02

0.66/0.02

0.66/0.02

ns

Minimum Pulse Width

T_{PWH_IO_FIFO}

RESET, RDCLK, WRCLK.

2.15

2.15

2.15

ns

T_{PWL_IO_FIFO}

RESET, RDCLK, WRCLK.

2.15

2.15

2.15

ns

Maximum Frequency

F_MAX

RDCLK and WRCLK.

200.00

200.00

200.00

MHz