Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that all standards meet their specifications. The selected standards are tested at a minimum VCCO with the respective VOL and VOH voltage levels shown. Other standards are sample tested.
|
I/O Standard |
VIL |
VIH |
VOL |
VOH |
IOL |
IOH |
||
|---|---|---|---|---|---|---|---|---|
|
V, Min |
V, Max |
V, Min |
V, Max |
V, Max |
V, Min |
mA, Max |
mA, Min |
|
|
HSTL_I |
–0.300 |
VREF – 0.100 |
VREF + 0.100 |
VCCO + 0.300 |
0.400 |
VCCO – 0.400 |
8.00 |
–8.00 |
|
HSTL_I_18 |
–0.300 |
VREF – 0.100 |
VREF + 0.100 |
VCCO + 0.300 |
0.400 |
VCCO – 0.400 |
8.00 |
–8.00 |
|
HSTL_II |
–0.300 |
VREF – 0.100 |
VREF + 0.100 |
VCCO + 0.300 |
0.400 |
VCCO – 0.400 |
16.00 |
–16.00 |
|
HSTL_II_18 |
–0.300 |
VREF – 0.100 |
VREF + 0.100 |
VCCO + 0.300 |
0.400 |
VCCO – 0.400 |
16.00 |
–16.00 |
|
HSUL_12 |
–0.300 |
VREF – 0.130 |
VREF + 0.130 |
VCCO + 0.300 |
20% VCCO |
80% VCCO |
0.10 |
–0.10 |
|
LVCMOS12 |
–0.300 |
35% VCCO |
65% VCCO |
VCCO + 0.300 |
0.400 |
VCCO – 0.400 |
||
|
LVCMOS15 |
–0.300 |
35% VCCO |
65% VCCO |
VCCO + 0.300 |
25% VCCO |
75% VCCO |
||
|
LVCMOS18 |
–0.300 |
35% VCCO |
65% VCCO |
VCCO + 0.300 |
0.450 |
VCCO – 0.450 |
||
|
LVCMOS25 |
–0.300 |
0.7 |
1.700 |
VCCO + 0.300 |
0.400 |
VCCO – 0.400 |
||
|
LVCMOS33 |
–0.300 |
0.8 |
2.000 |
3.450 |
0.400 |
VCCO – 0.400 |
||
|
LVTTL |
–0.300 |
0.8 |
2.000 |
3.450 |
0.400 |
2.400 |
||
|
MOBILE_DDR |
–0.300 |
20% VCCO |
80% VCCO |
VCCO + 0.300 |
10% VCCO |
90% VCCO |
0.10 |
–0.10 |
|
PCI33_3 |
–0.400 |
30% VCCO |
50% VCCO |
VCCO + 0.500 |
10% VCCO |
90% VCCO |
1.50 |
–0.50 |
|
SSTL135 |
–0.300 |
VREF – 0.090 |
VREF + 0.090 |
VCCO + 0.300 |
VCCO/2 – 0.150 |
VCCO/2 + 0.150 |
13.00 |
–13.00 |
|
SSTL135_R |
–0.300 |
VREF – 0.090 |
VREF + 0.090 |
VCCO + 0.300 |
VCCO/2 – 0.150 |
VCCO/2 + 0.150 |
8.90 |
–8.90 |
|
SSTL15 |
–0.300 |
VREF – 0.100 |
VREF + 0.100 |
VCCO + 0.300 |
VCCO/2 – 0.175 |
VCCO/2 + 0.175 |
13.00 |
–13.00 |
|
SSTL15_R |
–0.300 |
VREF – 0.100 |
VREF + 0.100 |
VCCO + 0.300 |
VCCO/2 – 0.175 |
VCCO/2 + 0.175 |
8.90 |
–8.90 |
|
SSTL18_I |
–0.300 |
VREF – 0.125 |
VREF + 0.125 |
VCCO + 0.300 |
VCCO/2 – 0.470 |
VCCO/2 + 0.470 |
8.00 |
–8.00 |
|
SSTL18_II |
–0.300 |
VREF – 0.125 |
VREF + 0.125 |
VCCO + 0.300 |
VCCO/2 – 0.600 |
VCCO/2 + 0.600 |
13.40 |
–13.40 |
|
Notes: 1.Tested according to relevant specifications. 2.3.3V and 2.5V standards are only supported in HR I/O banks. 3.For detailed interface specific DC voltage levels, see the 7\ Series FPGAs SelectIO Resources User Guide (UG471) [Ref 3]. 4.Supported drive strengths of 4, 8, or 12 mA in HR I/O banks. 5.Supported drive strengths of 4, 8, 12, or 16 mA in HR I/O banks. 6.Supported drive strengths of 4, 8, 12, 16, or 24 mA in HR I/O banks. |
||||||||
|
I/O Standard |
VICM(1) |
VID(2) |
VOCM(3) |
VOD(4) |
||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
V, Min |
V, Typ |
V, |
V, Min |
V, Typ |
V, Max |
V, |
V, |
V, |
V, Min |
V, Typ |
V, Max |
|
|
BLVDS_25 |
0.300 |
1.200 |
1.425 |
0.100 |
– |
– |
– |
1.250 |
– |
|||
|
MINI_LVDS_25 |
0.300 |
1.200 |
VCCAUX |
0.200 |
0.400 |
0.600 |
1.000 |
1.200 |
1.400 |
0.300 |
0.450 |
0.600 |
|
PPDS_25 |
0.200 |
0.900 |
VCCAUX |
0.100 |
0.250 |
0.400 |
0.500 |
0.950 |
1.400 |
0.100 |
0.250 |
0.400 |
|
RSDS_25 |
0.300 |
0.900 |
1.500 |
0.100 |
0.350 |
0.600 |
1.000 |
1.200 |
1.400 |
0.100 |
0.350 |
0.600 |
|
TMDS_33 |
2.700 |
2.965 |
3.230 |
0.150 |
0.675 |
1.200 |
VCCO – 0.405 |
VCCO – 0.300 |
VCCO – 0.190 |
0.400 |
0.600 |
0.800 |
|
Notes: 1.VICM is the input common mode voltage. 2.VID is the input differential voltage (Q – Q). 3.VOCM is the output common mode voltage. 4.VOD is the output differential voltage (Q – Q). 5.VOD for BLVDS will vary significantly depending on topology and loading. |
||||||||||||
|
I/O Standard |
VICM(1) |
VID(2) |
VOL(3) |
VOH(4) |
IOL |
IOH |
|||
|---|---|---|---|---|---|---|---|---|---|
|
V, Min |
V, Typ |
V, Max |
V, Min |
V, Max |
V, Max |
V, Min |
mA, Max |
mA, Min |
|
|
DIFF_HSTL_I |
0.300 |
0.750 |
1.125 |
0.100 |
– |
0.400 |
VCCO – 0.400 |
8.00 |
–8.00 |
|
DIFF_HSTL_I_18 |
0.300 |
0.900 |
1.425 |
0.100 |
– |
0.400 |
VCCO – 0.400 |
8.00 |
–8.00 |
|
DIFF_HSTL_II |
0.300 |
0.750 |
1.125 |
0.100 |
– |
0.400 |
VCCO – 0.400 |
16.00 |
–16.00 |
|
DIFF_HSTL_II_18 |
0.300 |
0.900 |
1.425 |
0.100 |
– |
0.400 |
VCCO – 0.400 |
16.00 |
–16.00 |
|
DIFF_HSUL_12 |
0.300 |
0.600 |
0.850 |
0.100 |
– |
20% VCCO |
80% VCCO |
0.100 |
–0.100 |
|
DIFF_MOBILE_DDR |
0.300 |
0.900 |
1.425 |
0.100 |
– |
10% VCCO |
90% VCCO |
0.100 |
–0.100 |
|
DIFF_SSTL135 |
0.300 |
0.675 |
1.000 |
0.100 |
– |
(VCCO/2) – 0.150 |
(VCCO/2) + 0.150 |
13.0 |
–13.0 |
|
DIFF_SSTL135_R |
0.300 |
0.675 |
1.000 |
0.100 |
– |
(VCCO/2) – 0.150 |
(VCCO/2) + 0.150 |
8.9 |
–8.9 |
|
DIFF_SSTL15 |
0.300 |
0.750 |
1.125 |
0.100 |
– |
(VCCO/2) – 0.175 |
(VCCO/2) + 0.175 |
13.0 |
–13.0 |
|
DIFF_SSTL15_R |
0.300 |
0.750 |
1.125 |
0.100 |
– |
(VCCO/2) – 0.175 |
(VCCO/2) + 0.175 |
8.9 |
–8.9 |
|
DIFF_SSTL18_I |
0.300 |
0.900 |
1.425 |
0.100 |
– |
(VCCO/2) – 0.470 |
(VCCO/2) + 0.470 |
8.00 |
–8.00 |
|
DIFF_SSTL18_II |
0.300 |
0.900 |
1.425 |
0.100 |
– |
(VCCO/2) – 0.600 |
(VCCO/2) + 0.600 |
13.4 |
–13.4 |
|
Notes: 1.VICM is the input common mode voltage. 2.VID is the input differential voltage (Q – Q). |
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