Table: IOB High Range (HR) Switching Characteristics summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays.
·TIOPI is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies depending on the capability of the SelectIO input buffer.
·TIOOP is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies depending on the capability of the SelectIO output buffer.
·TIOTP is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is disabled. The delay varies depending on the SelectIO capability of the output buffer. In HR I/O banks, the IN_TERM termination turn-on time is always faster than TIOTP when the INTERMDISABLE pin is used.
Table 17: IOB High Range (HR) Switching Characteristics
|
I/O Standard
|
TIOPI
|
TIOOP
|
TIOTP
|
Units
|
|
VCCINT Operating Voltage and Speed Grade
|
|
1.0V
|
0.95V
|
1.0V
|
0.95V
|
1.0V
|
0.95V
|
|
-2
|
-1
|
-1L
|
-2
|
-1
|
-1L
|
-2
|
-1
|
-1L
|
|
LVTTL_S4
|
1.34
|
1.41
|
1.41
|
3.93
|
4.18
|
4.18
|
3.96
|
4.20
|
4.20
|
ns
|
|
LVTTL_S8
|
1.34
|
1.41
|
1.41
|
3.66
|
3.92
|
3.92
|
3.69
|
3.93
|
3.93
|
ns
|
|
LVTTL_S12
|
1.34
|
1.41
|
1.41
|
3.65
|
3.90
|
3.90
|
3.68
|
3.91
|
3.91
|
ns
|
|
LVTTL_S16
|
1.34
|
1.41
|
1.41
|
3.19
|
3.45
|
3.45
|
3.22
|
3.46
|
3.46
|
ns
|
|
LVTTL_S24
|
1.34
|
1.41
|
1.41
|
3.41
|
3.67
|
3.67
|
3.44
|
3.68
|
3.68
|
ns
|
|
LVTTL_F4
|
1.34
|
1.41
|
1.41
|
3.38
|
3.64
|
3.64
|
3.41
|
3.65
|
3.65
|
ns
|
|
LVTTL_F8
|
1.34
|
1.41
|
1.41
|
2.87
|
3.12
|
3.12
|
2.90
|
3.13
|
3.13
|
ns
|
|
LVTTL_F12
|
1.34
|
1.41
|
1.41
|
2.85
|
3.10
|
3.10
|
2.88
|
3.12
|
3.12
|
ns
|
|
LVTTL_F16
|
1.34
|
1.41
|
1.41
|
2.68
|
2.93
|
2.93
|
2.71
|
2.95
|
2.95
|
ns
|
|
LVTTL_F24
|
1.34
|
1.41
|
1.41
|
2.65
|
2.90
|
2.90
|
2.68
|
2.91
|
2.91
|
ns
|
|
LVDS_25
|
0.81
|
0.88
|
0.88
|
1.41
|
1.67
|
1.67
|
1.44
|
1.68
|
1.68
|
ns
|
|
MINI_LVDS_25
|
0.81
|
0.88
|
0.88
|
1.40
|
1.65
|
1.65
|
1.43
|
1.66
|
1.66
|
ns
|
|
BLVDS_25
|
0.81
|
0.88
|
0.88
|
1.96
|
2.21
|
2.21
|
1.99
|
2.23
|
2.23
|
ns
|
|
RSDS_25 (point to point)
|
0.81
|
0.88
|
0.88
|
1.40
|
1.65
|
1.65
|
1.43
|
1.66
|
1.66
|
ns
|
|
PPDS_25
|
0.81
|
0.88
|
0.88
|
1.41
|
1.67
|
1.67
|
1.44
|
1.68
|
1.68
|
ns
|
|
TMDS_33
|
0.81
|
0.88
|
0.88
|
1.54
|
1.79
|
1.79
|
1.57
|
1.80
|
1.80
|
ns
|
|
PCI33_3
|
1.32
|
1.39
|
1.39
|
3.22
|
3.48
|
3.48
|
3.25
|
3.49
|
3.49
|
ns
|
|
HSUL_12_S
|
0.75
|
0.82
|
0.82
|
1.93
|
2.18
|
2.18
|
1.96
|
2.20
|
2.20
|
ns
|
|
HSUL_12_F
|
0.75
|
0.82
|
0.82
|
1.41
|
1.67
|
1.67
|
1.44
|
1.68
|
1.68
|
ns
|
|
DIFF_HSUL_12_S
|
0.76
|
0.83
|
0.83
|
1.93
|
2.18
|
2.18
|
1.96
|
2.20
|
2.20
|
ns
|
|
DIFF_HSUL_12_F
|
0.76
|
0.83
|
0.83
|
1.41
|
1.67
|
1.67
|
1.44
|
1.68
|
1.68
|
ns
|
|
MOBILE_DDR_S
|
0.84
|
0.91
|
0.91
|
1.80
|
2.06
|
2.06
|
1.83
|
2.07
|
2.07
|
ns
|
|
MOBILE_DDR_F
|
0.84
|
0.91
|
0.91
|
1.51
|
1.76
|
1.76
|
1.54
|
1.77
|
1.77
|
ns
|
|
DIFF_MOBILE_DDR_S
|
0.78
|
0.85
|
0.85
|
1.82
|
2.07
|
2.07
|
1.85
|
2.09
|
2.09
|
ns
|
|
DIFF_MOBILE_DDR_F
|
0.78
|
0.85
|
0.85
|
1.57
|
1.82
|
1.82
|
1.60
|
1.84
|
1.84
|
ns
|
|
HSTL_I_S
|
0.75
|
0.82
|
0.82
|
1.74
|
1.99
|
1.99
|
1.77
|
2.01
|
2.01
|
ns
|
|
HSTL_II_S
|
0.73
|
0.80
|
0.80
|
1.54
|
1.79
|
1.79
|
1.57
|
1.80
|
1.80
|
ns
|
|
HSTL_I_18_S
|
0.75
|
0.82
|
0.82
|
1.41
|
1.67
|
1.67
|
1.44
|
1.68
|
1.68
|
ns
|
|
HSTL_II_18_S
|
0.75
|
0.81
|
0.81
|
1.54
|
1.79
|
1.79
|
1.57
|
1.80
|
1.80
|
ns
|
|
DIFF_HSTL_I_S
|
0.76
|
0.83
|
0.83
|
1.71
|
1.96
|
1.96
|
1.74
|
1.98
|
1.98
|
ns
|
|
DIFF_HSTL_II_S
|
0.76
|
0.83
|
0.83
|
1.63
|
1.88
|
1.88
|
1.66
|
1.90
|
1.90
|
ns
|
|
DIFF_HSTL_I_18_S
|
0.79
|
0.86
|
0.86
|
1.51
|
1.76
|
1.76
|
1.54
|
1.77
|
1.77
|
ns
|
|
DIFF_HSTL_II_18_S
|
0.78
|
0.85
|
0.85
|
1.58
|
1.84
|
1.84
|
1.61
|
1.85
|
1.85
|
ns
|
|
HSTL_I_F
|
0.75
|
0.82
|
0.82
|
1.22
|
1.48
|
1.48
|
1.25
|
1.49
|
1.49
|
ns
|
|
HSTL_II_F
|
0.73
|
0.80
|
0.80
|
1.24
|
1.49
|
1.49
|
1.27
|
1.51
|
1.51
|
ns
|
|
HSTL_I_18_F
|
0.75
|
0.82
|
0.82
|
1.26
|
1.51
|
1.51
|
1.29
|
1.52
|
1.52
|
ns
|
|
HSTL_II_18_F
|
0.75
|
0.81
|
0.81
|
1.24
|
1.49
|
1.49
|
1.27
|
1.51
|
1.51
|
ns
|
|
DIFF_HSTL_I_F
|
0.76
|
0.83
|
0.83
|
1.30
|
1.56
|
1.56
|
1.33
|
1.57
|
1.57
|
ns
|
|
DIFF_HSTL_II_F
|
0.76
|
0.83
|
0.83
|
1.33
|
1.59
|
1.59
|
1.36
|
1.60
|
1.60
|
ns
|
|
DIFF_HSTL_I_18_F
|
0.79
|
0.86
|
0.86
|
1.33
|
1.59
|
1.59
|
1.36
|
1.60
|
1.60
|
ns
|
|
DIFF_HSTL_II_18_F
|
0.78
|
0.85
|
0.85
|
1.33
|
1.59
|
1.59
|
1.36
|
1.60
|
1.60
|
ns
|
|
LVCMOS33_S4
|
1.34
|
1.41
|
1.41
|
3.93
|
4.18
|
4.18
|
3.96
|
4.20
|
4.20
|
ns
|
|
LVCMOS33_S8
|
1.34
|
1.41
|
1.41
|
3.65
|
3.90
|
3.90
|
3.68
|
3.91
|
3.91
|
ns
|
|
LVCMOS33_S12
|
1.34
|
1.41
|
1.41
|
3.21
|
3.46
|
3.46
|
3.24
|
3.48
|
3.48
|
ns
|
|
LVCMOS33_S16
|
1.34
|
1.41
|
1.41
|
3.52
|
3.77
|
3.77
|
3.55
|
3.79
|
3.79
|
ns
|
|
LVCMOS33_F4
|
1.34
|
1.41
|
1.41
|
3.38
|
3.64
|
3.64
|
3.41
|
3.65
|
3.65
|
ns
|
|
LVCMOS33_F8
|
1.34
|
1.41
|
1.41
|
2.87
|
3.12
|
3.12
|
2.90
|
3.13
|
3.13
|
ns
|
|
LVCMOS33_F12
|
1.34
|
1.41
|
1.41
|
2.68
|
2.93
|
2.93
|
2.71
|
2.95
|
2.95
|
ns
|
|
LVCMOS33_F16
|
1.34
|
1.41
|
1.41
|
2.68
|
2.93
|
2.93
|
2.71
|
2.95
|
2.95
|
ns
|
|
LVCMOS25_S4
|
1.20
|
1.27
|
1.27
|
3.26
|
3.51
|
3.51
|
3.29
|
3.52
|
3.52
|
ns
|
|
LVCMOS25_S8
|
1.20
|
1.27
|
1.27
|
3.01
|
3.26
|
3.26
|
3.04
|
3.27
|
3.27
|
ns
|
|
LVCMOS25_S12
|
1.20
|
1.27
|
1.27
|
2.60
|
2.85
|
2.85
|
2.63
|
2.87
|
2.87
|
ns
|
|
LVCMOS25_S16
|
1.20
|
1.27
|
1.27
|
2.94
|
3.20
|
3.20
|
2.97
|
3.21
|
3.21
|
ns
|
|
LVCMOS25_F4
|
1.20
|
1.27
|
1.27
|
2.87
|
3.12
|
3.12
|
2.90
|
3.13
|
3.13
|
ns
|
|
LVCMOS25_F8
|
1.20
|
1.27
|
1.27
|
2.30
|
2.56
|
2.56
|
2.33
|
2.57
|
2.57
|
ns
|
|
LVCMOS25_F12
|
1.20
|
1.27
|
1.27
|
2.29
|
2.54
|
2.54
|
2.32
|
2.55
|
2.55
|
ns
|
|
LVCMOS25_F16
|
1.20
|
1.27
|
1.27
|
2.13
|
2.39
|
2.39
|
2.16
|
2.40
|
2.40
|
ns
|
|
LVCMOS18_S4
|
0.83
|
0.89
|
0.89
|
1.74
|
1.99
|
1.99
|
1.77
|
2.01
|
2.01
|
ns
|
|
LVCMOS18_S8
|
0.83
|
0.89
|
0.89
|
2.30
|
2.56
|
2.56
|
2.33
|
2.57
|
2.57
|
ns
|
|
LVCMOS18_S12
|
0.83
|
0.89
|
0.89
|
2.30
|
2.56
|
2.56
|
2.33
|
2.57
|
2.57
|
ns
|
|
LVCMOS18_S16
|
0.83
|
0.89
|
0.89
|
1.65
|
1.90
|
1.90
|
1.68
|
1.91
|
1.91
|
ns
|
|
LVCMOS18_S24
|
0.83
|
0.89
|
0.89
|
1.72
|
1.98
|
1.98
|
1.75
|
1.99
|
1.99
|
ns
|
|
LVCMOS18_F4
|
0.83
|
0.89
|
0.89
|
1.57
|
1.82
|
1.82
|
1.60
|
1.84
|
1.84
|
ns
|
|
LVCMOS18_F8
|
0.83
|
0.89
|
0.89
|
1.80
|
2.06
|
2.06
|
1.83
|
2.07
|
2.07
|
ns
|
|
LVCMOS18_F12
|
0.83
|
0.89
|
0.89
|
1.80
|
2.06
|
2.06
|
1.83
|
2.07
|
2.07
|
ns
|
|
LVCMOS18_F16
|
0.83
|
0.89
|
0.89
|
1.52
|
1.77
|
1.77
|
1.55
|
1.79
|
1.79
|
ns
|
|
LVCMOS18_F24
|
0.83
|
0.89
|
0.89
|
1.46
|
1.71
|
1.71
|
1.49
|
1.73
|
1.73
|
ns
|
|
LVCMOS15_S4
|
0.86
|
0.93
|
0.93
|
2.18
|
2.43
|
2.43
|
2.21
|
2.45
|
2.45
|
ns
|
|
LVCMOS15_S8
|
0.86
|
0.93
|
0.93
|
2.21
|
2.46
|
2.46
|
2.24
|
2.48
|
2.48
|
ns
|
|
LVCMOS15_S12
|
0.86
|
0.93
|
0.93
|
1.71
|
1.96
|
1.96
|
1.74
|
1.98
|
1.98
|
ns
|
|
LVCMOS15_S16
|
0.86
|
0.93
|
0.93
|
1.71
|
1.96
|
1.96
|
1.74
|
1.98
|
1.98
|
ns
|
|
LVCMOS15_F4
|
0.86
|
0.93
|
0.93
|
1.97
|
2.23
|
2.23
|
2.00
|
2.24
|
2.24
|
ns
|
|
LVCMOS15_F8
|
0.86
|
0.93
|
0.93
|
1.72
|
1.98
|
1.98
|
1.75
|
1.99
|
1.99
|
ns
|
|
LVCMOS15_F12
|
0.86
|
0.93
|
0.93
|
1.47
|
1.73
|
1.73
|
1.50
|
1.74
|
1.74
|
ns
|
|
LVCMOS15_F16
|
0.86
|
0.93
|
0.93
|
1.46
|
1.71
|
1.71
|
1.49
|
1.73
|
1.73
|
ns
|
|
LVCMOS12_S4
|
0.95
|
1.02
|
1.02
|
2.69
|
2.95
|
2.95
|
2.72
|
2.96
|
2.96
|
ns
|
|
LVCMOS12_S8
|
0.95
|
1.02
|
1.02
|
2.21
|
2.46
|
2.46
|
2.24
|
2.48
|
2.48
|
ns
|
|
LVCMOS12_S12
|
0.95
|
1.02
|
1.02
|
1.91
|
2.17
|
2.17
|
1.94
|
2.18
|
2.18
|
ns
|
|
LVCMOS12_F4
|
0.95
|
1.02
|
1.02
|
2.10
|
2.35
|
2.35
|
2.13
|
2.37
|
2.37
|
ns
|
|
LVCMOS12_F8
|
0.95
|
1.02
|
1.02
|
1.66
|
1.92
|
1.92
|
1.69
|
1.93
|
1.93
|
ns
|
|
LVCMOS12_F12
|
0.95
|
1.02
|
1.02
|
1.51
|
1.76
|
1.76
|
1.54
|
1.77
|
1.77
|
ns
|
|
SSTL135_S
|
0.75
|
0.82
|
0.82
|
1.47
|
1.73
|
1.73
|
1.50
|
1.74
|
1.74
|
ns
|
|
SSTL15_S
|
0.68
|
0.75
|
0.75
|
1.43
|
1.68
|
1.68
|
1.46
|
1.69
|
1.69
|
ns
|
|
SSTL18_I_S
|
0.75
|
0.82
|
0.82
|
1.79
|
2.04
|
2.04
|
1.82
|
2.06
|
2.06
|
ns
|
|
SSTL18_II_S
|
0.75
|
0.82
|
0.82
|
1.43
|
1.68
|
1.68
|
1.46
|
1.70
|
1.70
|
ns
|
|
DIFF_SSTL135_S
|
0.76
|
0.83
|
0.83
|
1.47
|
1.73
|
1.73
|
1.50
|
1.74
|
1.74
|
ns
|
|
DIFF_SSTL15_S
|
0.76
|
0.83
|
0.83
|
1.43
|
1.68
|
1.68
|
1.46
|
1.69
|
1.69
|
ns
|
|
DIFF_SSTL18_I_S
|
0.79
|
0.86
|
0.86
|
1.80
|
2.06
|
2.06
|
1.83
|
2.07
|
2.07
|
ns
|
|
DIFF_SSTL18_II_S
|
0.79
|
0.86
|
0.86
|
1.51
|
1.76
|
1.76
|
1.54
|
1.77
|
1.77
|
ns
|
|
SSTL135_F
|
0.75
|
0.82
|
0.82
|
1.24
|
1.49
|
1.49
|
1.27
|
1.51
|
1.51
|
ns
|
|
SSTL15_F
|
0.68
|
0.75
|
0.75
|
1.19
|
1.45
|
1.45
|
1.22
|
1.46
|
1.46
|
ns
|
|
SSTL18_I_F
|
0.75
|
0.82
|
0.82
|
1.24
|
1.49
|
1.49
|
1.27
|
1.51
|
1.51
|
ns
|
|
SSTL18_II_F
|
0.75
|
0.82
|
0.82
|
1.24
|
1.49
|
1.49
|
1.27
|
1.51
|
1.51
|
ns
|
|
DIFF_SSTL135_F
|
0.76
|
0.83
|
0.83
|
1.24
|
1.49
|
1.49
|
1.27
|
1.51
|
1.51
|
ns
|
|
DIFF_SSTL15_F
|
0.76
|
0.83
|
0.83
|
1.19
|
1.45
|
1.45
|
1.22
|
1.46
|
1.46
|
ns
|
|
DIFF_SSTL18_I_F
|
0.79
|
0.86
|
0.86
|
1.35
|
1.60
|
1.60
|
1.38
|
1.62
|
1.62
|
ns
|
|
DIFF_SSTL18_II_F
|
0.79
|
0.86
|
0.86
|
1.33
|
1.59
|
1.59
|
1.36
|
1.60
|
1.60
|
ns
|
Table: IOB 3-state Output Switching Characteristics specifies the values of TIOTPHZ and TIOIBUFDISABLE. TIOTPHZ is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state). TIOIBUFDISABLE is described as the IOB delay from IBUFDISABLE to O output. In HR I/O banks, the internal IN_TERM termination turn-off time is always faster than TIOTPHZ when the INTERMDISABLE pin is used.
Table 18: IOB 3-state Output Switching Characteristics
|
Symbol
|
Description
|
VCCINT Operating Voltage and Speed Grade
|
Units
|
|
1.0V
|
0.95V
|
|
-2
|
-1
|
-1L
|
|
TIOTPHZ
|
T input to pad high-impedance.
|
2.19
|
2.37
|
2.37
|
ns
|
|
TIOIBUFDISABLE
|
IBUF turn-on time from IBUFDISABLE to O output.
|
2.30
|
2.60
|
2.60
|
ns
|