DC Characteristics

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS189)
Document ID
DS189
Release Date
2022-10-31
Revision
1.10 English
Table  1:   Absolute Maximum Ratings(1)

Symbol

Description

Min

Max

Units

FPGA Logic

VCCINT

Internal supply voltage.

–0.5

1.1

V

VCCAUX

Auxiliary supply voltage.

–0.5

2.0

V

VCCBRAM

Supply voltage for the block RAM memories.

–0.5

1.1

V

VCCO

Output drivers supply voltage for HR I/O banks.

–0.5

3.6

V

VREF

Input reference voltage.

–0.5

2.0

V

VIN(2)(3)(4)

I/O input voltage.

–0.4

VCCO + 0.55

V

I/O input voltage (when VCCO = 3.3V) for VREF and differential I/O standards except TMDS_33.(5)

–0.4

2.625

V

VCCBATT

Key memory battery backup supply.

–0.5

2.0

V

XADC

VCCADC

XADC supply relative to GNDADC.

–0.5

2.0

V

VREFP

XADC reference input relative to GNDADC.

–0.5

2.0

V

Temperature

TSTG

Storage temperature (ambient).

–65

150

°C

TSOL

Maximum soldering temperature for Pb/Sn component bodies.(6)

–

+220

°C

Maximum soldering temperature for Pb-free component bodies.(6)

–

+260

°C

Tj

Maximum junction temperature.(6)

–

+125

°C

Notes:

1.Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.

2.The lower absolute voltage specification always applies.

3.For I/O operation, refer to the 7\ Series FPGAs SelectIO Resources User Guide (UG471) [Ref 3].

4.The maximum limit applies to DC signals. For maximum undershoot and overshoot AC specifications, see Table: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HR I/O Banks(1)(2).

5.See Table: Differential SelectIO DC Input and Output Levels for TMDS_33 specifications.

6.For soldering guidelines and thermal considerations, see the 7 Series FPGA Packaging and Pinout Specification (UG475) [Ref 4].
Table  2:   Recommended Operating Conditions(1)(2)

Symbol

Description

Min

Typ

Max

Units

FPGA Logic

VCCINT(3)

For -2 and -1 (1.0V) devices: internal supply voltage.

0.95

1.00

1.05

V

For -1L (0.95V) devices: internal supply voltage.

0.92

0.95

0.98

V

VCCAUX

Auxiliary supply voltage.

1.71

1.80

1.89

V

VCCBRAM(3)

For -2 and -1 (1.0V) devices: block RAM supply voltage.

0.95

1.00

1.05

V

For -1L (0.95V) devices: block RAM supply voltage.

0.92

0.95

0.98

V

VCCO(4)(5)

Supply voltage for HR I/O banks.

1.14

–

3.465

V

VIN(6)

I/O input voltage.

–0.20

–

VCCO + 0.20

V

I/O input voltage (when VCCO = 3.3V) for VREF and differential I/O standards except TMDS_33.(7)

–0.20

–

2.625

V

IIN(8)

Maximum current through any pin in a powered or unpowered bank when forward biasing the clamp diode.

–

–

10

mA

VCCBATT(9)

Battery voltage.

1.0

–

1.89

V

XADC

VCCADC

XADC supply relative to GNDADC.

1.71

1.80

1.89

V

VREFP

Externally supplied reference voltage.

1.20

1.25

1.30

V

Temperature

Tj

Junction temperature operating range for commercial (C) temperature devices.

0

–

85

°C

Junction temperature operating range for industrial (I) temperature devices.

–40

–

100

°C

Junction temperature operating range for expanded (Q)

temperature devices.

–40

–

125

°C

Notes:

1.All voltages are relative to ground.

2.For the design of the power distribution system consult the 7 Series FPGAs PCB Design Guide (UG483) [Ref 5].

3.If VCCINT and VCCBRAM are operating at the same voltage, VCCINT and VCCBRAM should be connected to the same supply.

4.Configuration data is retained even if VCCO drops to 0V.

5.Includes VCCO of 1.2V, 1.35V, 1.5V, 1.8V, 2.5V, and 3.3V at ±5%.

6.The lower absolute voltage specification always applies.

7.See Table: Differential SelectIO DC Input and Output Levels for TMDS_33 specifications.

8.A total of 200 mA per bank should not be exceeded.

9.VCCBATT is required only when using bitstream encryption. If battery is not used, connect VCCBATT to either ground or VCCAUX.
Table  3:   DC Characteristics Over Recommended Operating Conditions

Symbol

Description

Min

Typ(1)

Max

Units

VDRINT

Data retention VCCINT voltage (below which configuration data might be lost).

0.75

–

–

V

VDRI

Data retention VCCAUX voltage (below which configuration data might be lost).

1.5

–

–

V

IREF

VREF leakage current per pin.

–

–

15

µA

IL

Input or output leakage current per pin (sample-tested).

–

–

15

µA

CIN(2)

Die input capacitance at the pad.

–

–

8

pF

IRPU

Pad pull-up (when selected) at VIN = 0V, VCCO = 3.3V.

90

–

330

µA

Pad pull-up (when selected) at VIN = 0V, VCCO = 2.5V.

68

–

250

µA

Pad pull-up (when selected) at VIN = 0V, VCCO = 1.8V.

34

–

220

µA

Pad pull-up (when selected) at VIN = 0V, VCCO = 1.5V.

23

–

150

µA

Pad pull-up (when selected) at VIN = 0V, VCCO = 1.2V.

12

–

120

µA

IRPD

Pad pull-down (when selected) at VIN = 3.3V.

68

–

330

µA

ICCADC

Analog supply current, analog circuits in powered up state.

–

–

25

mA

IBATT(3)

Battery supply current.

–

–

150

nA

RIN_TERM(4)

Thevenin equivalent resistance of programmable input termination to VCCO/2 (UNTUNED_SPLIT_40).

28

40

55

W

Thevenin equivalent resistance of programmable input termination to VCCO/2 (UNTUNED_SPLIT_50).

35

50

65

W

Thevenin equivalent resistance of programmable input termination to VCCO/2 (UNTUNED_SPLIT_60).

44

60

83

W

n

Temperature diode ideality factor.

–

1.010

–

–

r

Temperature diode series resistance.

–

2

–

W

Notes:

1.Typical values are specified at nominal voltage, 25°C.

2.This measurement represents the die capacitance at the pad, not including the package.

3.Maximum value specified for worst case process at 25°C.

4.Termination resistance to a VCCO/2 level.
Table  4:   VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HR I/O Banks(1)(2)

AC Voltage Overshoot

% of UI at –40°C to 125°C

AC Voltage Undershoot

% of UI at –40°C to 125°C

VCCO + 0.55

100

–0.40

100

–0.45

61.7

–0.50

25.8

–0.55

11.0

VCCO + 0.60

46.6

–0.60

4.77

VCCO + 0.65

21.2

–0.65

2.10

VCCO + 0.70

9.75

–0.70

0.94

VCCO + 0.75

4.55

–0.75

0.43

VCCO + 0.80

2.15

–0.80

0.20

VCCO + 0.85

1.02

–0.85

0.09

VCCO + 0.90

0.49

–0.90

0.04

VCCO + 0.95

0.24

–0.95

0.02

Notes:

1.A total of 200 mA per bank should not be exceeded.

2.The peak voltage of the overshoot or undershoot, and the duration above VCCO + 0.20V or below GND – 0.20V, must not exceed the values in this table.
Table  5:   Typical Quiescent Supply Current(1)(2)(3)

Symbol

Description

Device

Speed Grade

Units

1.0V

0.95V

-2C

-2I

-1C

-1I

-1Q

-1LI

ICCINTQ

Quiescent VCCINT supply current.

XC7S6

36

36

36

36

36

32

mA

XC7S15

36

36

36

36

36

32

mA

XC7S25

48

48

48

48

48

43

mA

XC7S50

95

95

95

95

95

59

mA

XC7S75

148

148

148

148

148

134

mA

XC7S100

148

148

148

148

148

134

mA

XA7S6

N/A

36

N/A

36

36

N/A

mA

XA7S15

N/A

36

N/A

36

36

N/A

mA

XA7S25

N/A

48

N/A

48

48

N/A

mA

XA7S50

N/A

95

N/A

95

95

N/A

mA

XA7S75

N/A

148

N/A

148

148

N/A

mA

XA7S100

N/A

148

N/A

148

148

N/A

mA

ICCOQ

Quiescent VCCO supply current.

XC7S6

1

1

1

1

1

1

mA

XC7S15

1

1

1

1

1

1

mA

XC7S25

1

1

1

1

1

1

mA

XC7S50

1

1

1

1

1

1

mA

XC7S75

4

4

4

4

4

4

mA

XC7S100

4

4

4

4

4

4

mA

XA7S6

N/A

1

N/A

1

1

N/A

mA

XA7S15

N/A

1

N/A

1

1

N/A

mA

XA7S25

N/A

1

N/A

1

1

N/A

mA

XA7S50

N/A

1

N/A

1

1

N/A

mA

XA7S75

N/A

4

N/A

4

4

N/A

mA

XA7S100

N/A

4

N/A

4

4

N/A

mA

ICCAUXQ

Quiescent VCCAUX supply current.

XC7S6

10

10

10

10

10

10

mA

XC7S15

10

10

10

10

10

10

mA

XC7S25

13

13

13

13

13

13

mA

XC7S50

22

22

22

22

22

20

mA

XC7S75

43

43

43

43

43

43

mA

XC7S100

43

43

43

43

43

43

mA

XA7S6

N/A

10

N/A

10

10

N/A

mA

XA7S15

N/A

10

N/A

10

10

N/A

mA

XA7S25

N/A

13

N/A

13

13

N/A

mA

XA7S50

N/A

22

N/A

22

22

N/A

mA

XA7S75

N/A

43

N/A

43

43

N/A

mA

XA7S100

N/A

43

N/A

43

43

N/A

mA

ICCBRAMQ

Quiescent VCCBRAM supply current.

XC7S6

1

1

1

1

1

1

mA

XC7S15

1

1

1

1

1

1

mA

XC7S25

1

1

1

1

1

1

mA

XC7S50

2

2

2

2

2

1

mA

XC7S75

9

9

9

9

9

8

mA

XC7S100

9

9

9

9

9

8

mA

XA7S6

N/A

1

N/A

1

1

N/A

mA

XA7S15

N/A

1

N/A

1

1

N/A

mA

XA7S25

N/A

1

N/A

1

1

N/A

mA

XA7S50

N/A

2

N/A

2

2

N/A

mA

XA7S75

N/A

9

N/A

9

9

N/A

mA

XA7S100

N/A

9

N/A

9

9

N/A

mA

Notes:

1.Typical values are specified at nominal voltage, 85°C junction temperature (Tj) with single-ended SelectIO™ resources.

2.Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating.

3.Use the Xilinx Power Estimator spreadsheet tool [Ref 6] to estimate static power consumption for conditions other than those specified.