Device Pin-to-Pin Output Parameter Guidelines

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS189)

Document ID
DS189
Release Date
2022-10-31
Revision
1.10 English
Table  39:   Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Near Clock Region)(1)

Symbol

Description

Device

VCCINT Operating Voltage and Speed Grade

Units

1.0V

0.95V

-2

-1

-1L

SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM/PLL.

TICKOF

Clock-capable clock input and OUTFF at pins/banks closest to the BUFGs without MMCM/PLL (near clock region).(2)

XC7S6

5.55

6.50

6.50

ns

XC7S15

5.55

6.50

6.50

ns

XC7S25

5.55

6.44

6.44

ns

XC7S50

5.71

6.62

6.62

ns

XC7S75

5.73

6.71

6.71

ns

XC7S100

5.73

6.71

6.71

ns

XA7S6

5.55

6.50

N/A

ns

XA7S15

5.55

6.50

N/A

ns

XA7S25

5.55

6.44

N/A

ns

XA7S50

5.71

6.62

N/A

ns

XA7S75

5.73

6.71

N/A

ns

XA7S100

5.73

6.71

N/A

ns

Notes:

1.This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net.

2.Refer to the Die Level Bank Numbering Overview section of the 7 Series FPGA Packaging and Pinout Specification (UG475) [Ref 4].

Table  40:   Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Far Clock Region)(1)

Symbol

Description

Device

VCCINT Operating Voltage and Speed Grade

Units

1.0V

0.95V

-2

-1

-1L

SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM/PLL.

TICKOFFAR

Clock-capable clock input and OUTFF at pins/banks farthest from the BUFGs without MMCM/PLL (far clock region).(2)

XC7S6

5.55

6.50

6.50

ns

XC7S15

5.55

6.50

6.50

ns

XC7S25

5.55

6.44

6.44

ns

XC7S50

5.71

6.62

6.62

ns

XC7S75

6.01

7.02

7.02

ns

XC7S100

6.01

7.02

7.02

ns

XA7S6

5.55

6.50

N/A

ns

XA7S15

5.55

6.50

N/A

ns

XA7S25

5.55

6.44

N/A

ns

XA7S50

5.71

6.62

N/A

ns

XA7S75

6.01

7.02

N/A

ns

XA7S100

6.01

7.02

N/A

ns

Notes:

1.This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net.

2.Refer to the Die Level Bank Numbering Overview section of the 7 Series FPGA Packaging and Pinout Specification (UG475) [Ref 4].

Table  41:   Clock-Capable Clock Input to Output Delay With MMCM(1)

Symbol

Description

Device

VCCINT Operating Voltage and Speed Grade

Units

1.0V

0.95V

-2

-1

-1L

SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with MMCM.

TICKOFMMCMCC

Clock-capable clock input and OUTFF with MMCM.(2)

XC7S6

1.03

1.03

1.03

ns

XC7S15

1.03

1.03

1.03

ns

XC7S25

1.00

1.00

1.00

ns

XC7S50

1.00

1.00

1.00

ns

XC7S75

1.00

1.00

1.00

ns

XC7S100

1.00

1.00

1.00

ns

XA7S6

1.03

1.03

N/A

ns

XA7S15

1.03

1.03

N/A

ns

XA7S25

1.00

1.00

N/A

ns

XA7S50

1.00

1.00

N/A

ns

XA7S75

1.00

1.00

N/A

ns

XA7S100

1.00

1.00

N/A

ns

Notes:

1.This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net.

2.MMCM output jitter is already included in the timing calculation.

Table  42:   Clock-Capable Clock Input to Output Delay With PLL(1)

Symbol

Description

Device

VCCINT Operating Voltage and Speed Grade

Units

1.0V

0.95V

-2

-1

-1L

SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with PLL.

TICKOFPLLCC

Clock-capable clock input and OUTFF with PLL.(2)

XC7S6

0.85

0.85

0.85

ns

XC7S15

0.85

0.85

0.85

ns

XC7S25

0.83

0.83

0.83

ns

XC7S50

0.83

0.83

0.83

ns

XC7S75

0.83

0.83

0.83

ns

XC7S100

0.83

0.83

0.83

ns

XA7S6

0.85

0.85

N/A

ns

XA7S15

0.85

0.85

N/A

ns

XA7S25

0.83

0.83

N/A

ns

XA7S50

0.83

0.83

N/A

ns

XA7S75

0.83

0.83

N/A

ns

XA7S100

0.83

0.83

N/A

ns

Notes:

1.This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net.

2.PLL output jitter is already included in the timing calculation.

Table  43:   Pin-to-Pin, Clock-to-Out using BUFIO

Symbol

Description

VCCINT Operating Voltage and Speed Grade

Units

1.0V

0.95V

-2

-1

-1L

SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with BUFIO.

TICKOFCS

Clock to out of I/O clock.

5.61

6.64

6.64

ns