Symbol | Description | VCCINT Operating Voltage and Speed Grade | Units | ||
|---|---|---|---|---|---|
1.0V | 0.95V | ||||
-2 | -1 | -1L | |||
Power-up Timing Characteristics | |||||
TPL(1) | Program latency. | 5.00 | 5.00 | 5.00 | ms, Max |
TPOR(2) | Power-on reset | 10/50 | 10/50 | 10/50 | ms, Min/Max |
Power-on reset | 10/35 | 10/35 | 10/35 | ms, Min/Max | |
TPROGRAM | Program pulse width. | 250.00 | 250.00 | 250.00 | ns, Min |
CCLK Output (Master Mode) | |||||
TICCK | Master CCLK output delay. | 150.00 | 150.00 | 150.00 | ns, Min |
TMCCKL | Master CCLK clock Low time duty cycle. | 40/60 | 40/60 | 40/60 | %, Min/Max |
TMCCKH | Master CCLK clock High time duty cycle. | 40/60 | 40/60 | 40/60 | %, Min/Max |
FMCCK | Master CCLK frequency. | 100.00 | 100.00 | 100.00 | MHz, Max |
Master CCLK frequency for AES encrypted x16.(2) | 50.00 | 50.00 | 50.00 | MHz, Max | |
FMCCK_START | Master CCLK frequency at start of configuration. | 3.00 | 3.00 | 3.00 | MHz, Typ |
FMCCKTOL | Frequency tolerance, master mode with respect to nominal CCLK. | ±50 | ±50 | ±50 | %, Max |
CCLK Input (Slave Modes) | |||||
TSCCKL | Slave CCLK clock minimum Low time. | 2.50 | 2.50 | 2.50 | ns, Min |
TSCCKH | Slave CCLK clock minimum High time. | 2.50 | 2.50 | 2.50 | ns, Min |
FSCCK | Slave CCLK frequency. | 100.00 | 100.00 | 100.00 | MHz, Max |
EMCCLK Input (Master Mode) | |||||
TEMCCKL | External master CCLK Low time. | 2.50 | 2.50 | 2.50 | ns, Min |
TEMCCKH | External master CCLK High time. | 2.50 | 2.50 | 2.50 | ns, Min |
FEMCCK | External master CCLK frequency. | 100.00 | 100.00 | 100.00 | MHz, Max |
Internal Configuration Access Port | |||||
FICAPCK | Internal configuration access port (ICAPE2) clock frequency. | 100.00 | 100.00 | 100.00 | MHz, Max |
Master/Slave Serial Mode Programming Switching | |||||
TDCCK/ TCCKD | DIN setup/hold. | 4.00/0.00 | 4.00/0.00 | 4.00/0.00 | ns, Min |
TCCO | DOUT clock to out. | 8.00 | 8.00 | 8.00 | ns, Max |
SelectMAP Mode Programming Switching | |||||
TSMDCCK/ TSMCCKD | D[31:00] setup/hold. | 4.00/0.00 | 4.00/0.00 | 4.00/0.00 | ns, Min |
TSMCSCCK/ TSMCCKCS | CSI_B setup/hold. | 4.00/0.00 | 4.00/0.00 | 4.00/0.00 | ns, Min |
TSMWCCK/ TSMCCKW | RDWR_B setup/hold. | 10.00/0.00 | 10.00/0.00 | 10.00/0.00 | ns, Min |
TSMCKCSO | CSO_B clock to out (330 W pull-up resistor required). | 7.00 | 7.00 | 7.00 | ns, Max |
TSMCO | D[31:00] clock to out in readback. | 8.00 | 8.00 | 8.00 | ns, Max |
FRBCCK | Readback frequency. | 100.00 | 100.00 | 100.00 | MHz, Max |
Boundary-Scan Port Timing Specifications | |||||
TTAPTCK/ TTCKTAP | TMS and TDI setup/hold. | 3.00/2.00 | 3.00/2.00 | 3.00/2.00 | ns, Min |
TTCKTDO | TCK falling edge to TDO output. | 7.00 | 7.00 | 7.00 | ns, Max |
FTCK | TCK frequency. | 66.00 | 66.00 | 66.00 | MHz, Max |
SPI Flash Master Mode Programming Switching | |||||
TSPIDCC/ TSPICCD | D[03:00] setup/hold. | 3.00/0.00 | 3.00/0.00 | 3.00/0.00 | ns, Min |
TSPICCM | MOSI clock to out. | 8.00 | 8.00 | 8.00 | ns, Max |
TSPICCFC | FCS_B clock to out. | 8.00 | 8.00 | 8.00 | ns, Max |
STARTUPE2 Ports | |||||
TUSRCCLKO | STARTUPE2 USRCCLKO input to CCLK output. | 0.50/6.70 | 0.50/7.50 | 0.50/7.50 | ns, Min/Max |
FCFGMCLK | STARTUPE2 CFGMCLK output frequency. | 65.00 | 65.00 | 65.00 | MHz, Typ |
FCFGMCLKTOL | STARTUPE2 CFGMCLK output frequency tolerance. | ±50 | ±50 | ±50 | %, Max |
Device DNA Access Port | |||||
FDNACK | DNA access port (DNA_PORT). | 100.00 | 100.00 | 100.00 | MHz, Max |
Notes: 1.To support longer delays in configuration, use the design solutions described in the 7 Series FPGA Configuration User Guide (UG470) [Ref 10]. 2.See the 7 Series FPGAs Overview (DS180) [Ref 1] and XA Spartan 7 Automotive FPGA Data Sheet: Overview (DS171) [Ref 2] for a list of devices that support bitstream encryption. | |||||