Output delays are measured with short output traces. Standard termination was used for all testing. The propagation delay of the trace is characterized separately and subtracted from the final measurement, and is therefore not included in the generalized test setups shown in This Figure and This Figure.
Parameters VREF, RREF, CREF, and VMEAS fully describe the test conditions for each I/O standard. The most accurate prediction of propagation delay in any given application can be obtained through IBIS simulation, using this method:
1.Simulate the output driver of choice into the generalized test setup using values from Table: Output Delay Measurement Methodology.
2.Record the time to VMEAS.
3.Simulate the output driver of choice into the actual PCB trace and load using the appropriate IBIS model or capacitance value to represent the load.
4.Record the time to VMEAS.
5.Compare the results of step 2 and step 4. The increase or decrease in delay yields the actual propagation delay of the PCB trace.
I/O Standard Attribute | RREF (W) | CREF(1) (pF) | VMEAS (V) | VREF (V) | |
|---|---|---|---|---|---|
LVCMOS, 1.2V | LVCMOS12 | 1M | 0 | 0.6 | 0 |
LVCMOS, 1.5V | LVCMOS15 | 1M | 0 | 0.75 | 0 |
LVCMOS, 1.8V | LVCMOS18 | 1M | 0 | 0.9 | 0 |
LVCMOS, 2.5V | LVCMOS25 | 1M | 0 | 1.25 | 0 |
LVCMOS, 3.3V | LVCMOS33 | 1M | 0 | 1.65 | 0 |
LVTTL, 3.3V | LVTTL | 1M | 0 | 1.65 | 0 |
PCI33, 3.3V | PCI33_3 | 25 | 10 | 1.65 | 0 |
HSTL (high-speed transceiver logic), Class I, 1.2V | HSTL_I_12 | 50 | 0 | VREF | 0.6 |
HSTL, Class I, 1.5V | HSTL_I | 50 | 0 | VREF | 0.75 |
HSTL, Class II, 1.5V | HSTL_II | 25 | 0 | VREF | 0.75 |
HSTL, Class I, 1.8V | HSTL_I_18 | 50 | 0 | VREF | 0.9 |
HSTL, Class II, 1.8V | HSTL_II_18 | 25 | 0 | VREF | 0.9 |
HSUL (high-speed unterminated logic), 1.2V | HSUL_12 | 50 | 0 | VREF | 0.6 |
SSTL12, 1.2V | SSTL12 | 50 | 0 | VREF | 0.6 |
SSTL135/SSTL135_R, 1.35V | SSTL135, SSTL135_R | 50 | 0 | VREF | 0.675 |
SSTL15/SSTL15_R, 1.5V | SSTL15, SSTL15_R | 50 | 0 | VREF | 0.75 |
SSTL (stub-series terminated logic), | SSTL18_I, SSTL18_II | 50 | 0 | VREF | 0.9 |
DIFF_MOBILE_DDR, 1.8V | DIFF_MOBILE_DDR | 50 | 0 | VREF | 0.9 |
DIFF_HSTL, Class I, 1.2V | DIFF_HSTL_I_12 | 50 | 0 | VREF | 0.6 |
DIFF_HSTL, Class I & II, 1.5V | DIFF_HSTL_I, DIFF_HSTL_II | 50 | 0 | VREF | 0.75 |
DIFF_HSTL, Class I & II, 1.8V | DIFF_HSTL_I_18, DIFF_HSTL_II_18 | 50 | 0 | VREF | 0.9 |
DIFF_HSUL_12, 1.2V | DIFF_HSUL_12 | 50 | 0 | VREF | 0.6 |
DIFF_SSTL135/DIFF_SSTL135_R, 1.35V | DIFF_SSTL135, DIFF_SSTL135_R | 50 | 0 | VREF | 0.675 |
DIFF_SSTL15/DIFF_SSTL15_R, 1.5V | DIFF_SSTL15, DIFF_SSTL15_R | 50 | 0 | VREF | 0.75 |
DIFF_SSTL18, Class I & II, 1.8V | DIFF_SSTL18_I, DIFF_SSTL18_II | 50 | 0 | VREF | 0.9 |
LVDS, 2.5V | LVDS_25 | 100 | 0 | 0(2) | 0 |
BLVDS (Bus LVDS), 2.5V | BLVDS_25 | 100 | 0 | 0(2) | 0 |
Mini LVDS, 2.5V | MINI_LVDS_25 | 100 | 0 | 0(2) | 0 |
PPDS_25 | PPDS_25 | 100 | 0 | 0(2) | 0 |
RSDS_25 | RSDS_25 | 100 | 0 | 0(2) | 0 |
TMDS_33 | TMDS_33 | 50 | 0 | 0(2) | 3.3 |
Notes: 1.CREF is the capacitance of the probe, nominally 0 pF. | |||||