Power-On/Off Power Supply Sequencing

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS189)

Document ID
DS189
Release Date
2022-10-31
Revision
1.10 English

The recommended power-on sequence is VCCINT, VCCBRAM, VCCAUX, and VCCO to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-on sequence. If VCCINT and VCCBRAM have the same recommended voltage levels then both can be powered by the same supply and ramped simultaneously. If VCCAUX and VCCO have the same recommended voltage levels then both can be powered by the same supply and ramped simultaneously.

For VCCO voltages of 3.3V in HR I/O banks and configuration bank 0 the following conditions apply.

·The voltage difference between VCCO and VCCAUX must not exceed 2.625V for longer than TVCCO2VCCAUX for each power-on/off cycle to maintain device reliability levels.

·The TVCCO2VCCAUX time can be allocated in any percentage between the power-on and power-off ramps.

There is no recommended sequence for supplies not discussed in this section.

Table: Power-On Current shows the minimum current, in addition to ICCQ maximum, that is required by Spartan-7 devices for proper power-on and configuration. If the current minimums shown in Table: Power-On Current are met, the device powers on after all four supplies have passed through their power-on reset threshold voltages. The FPGA must not be configured until after VCCINT is applied. Once initialized and configured, use the Xilinx Power Estimator spreadsheet tool [Ref 6] to estimate current drain on these supplies.

Table  6:   Power-On Current

Device

ICCINTMIN

ICCAUXMIN

ICCOMIN

ICCBRAMMIN

Units

XC7S6

ICCINTQ + 120

ICCAUXQ + 40

ICCOQ + 40 mA per bank

ICCBRAMQ + 60

mA

XC7S15

ICCINTQ + 120

ICCAUXQ + 40

ICCOQ + 40 mA per bank

ICCBRAMQ + 60

mA

XC7S25

ICCINTQ + 120

ICCAUXQ + 40

ICCOQ + 40 mA per bank

ICCBRAMQ + 60

mA

XC7S50

ICCINTQ + 120

ICCAUXQ + 40

ICCOQ + 40 mA per bank

ICCBRAMQ + 60

mA

XC7S75

ICCINTQ + 300

ICCAUXQ + 140

ICCOQ + 40 mA per bank

ICCBRAMQ + 60

mA

XC7S100

ICCINTQ + 300

ICCAUXQ + 140

ICCOQ + 40 mA per bank

ICCBRAMQ + 60

mA

XA7S6

ICCINTQ + 120

ICCAUXQ + 40

ICCOQ + 40 mA per bank

ICCBRAMQ + 60

mA

XA7S15

ICCINTQ + 120

ICCAUXQ + 40

ICCOQ + 40 mA per bank

ICCBRAMQ + 60

mA

XA7S25

ICCINTQ + 120

ICCAUXQ + 40

ICCOQ + 40 mA per bank

ICCBRAMQ + 60

mA

XA7S50

ICCINTQ + 120

ICCAUXQ + 40

ICCOQ + 40 mA per bank

ICCBRAMQ + 60

mA

XA7S75

ICCINTQ + 300

ICCAUXQ + 140

ICCOQ + 40 mA per bank

ICCBRAMQ + 60

mA

XA7S100

ICCINTQ + 300

ICCAUXQ + 140

ICCOQ + 40 mA per bank

ICCBRAMQ + 60

mA

Table  7:   Power Supply Ramp Time

Symbol

Description

Conditions

Min

Max

Units

TVCCINT

Ramp time from GND to 90% of VCCINT.

0.2

50

ms

TVCCO

Ramp time from GND to 90% of VCCO.

0.2

50

ms

TVCCAUX

Ramp time from GND to 90% of VCCAUX.

0.2

50

ms

TVCCBRAM

Ramp time from GND to 90% of VCCBRAM.

0.2

50

ms

TVCCO2VCCAUX

Allowed time per power cycle for VCCO – VCCAUX > 2.625V.

TJ = 125°C(1)

300

ms

TJ = 100°C(1)

500

ms

TJ = 85°C(1)

800

ms

Notes:

1.Based on 240,000 power cycles with a nominal VCCO of 3.3V or 36,500 power cycles with a worst case VCCO of 3.465V.