LVDS DC Specifications (LVDS_25)

V_CCO

Supply voltage.

2.375

2.500

2.625

V

V_OH

Output High voltage for Q and Q.

R_T = 100W across Q and Q signals.

–

–

1.675

V

V_OL

Output Low voltage for Q and Q.

R_T = 100W across Q and Q signals.

0.700

–

–

V

V_ODIFF

Differential output voltage:

(Q – Q), Q = High

(Q – Q), Q = High

R_T = 100W across Q and Q signals.

247

350

600

mV

V_OCM

Output common-mode voltage.

R_T = 100W across Q and Q signals.

1.000

1.250

1.425

V

V_IDIFF

Differential input voltage:

(Q – Q), Q = High

(Q – Q), Q = High

100

350

600

mV

V_ICM

Input common-mode voltage.

0.300

1.200

1.500

V

Notes:

1.​Differential inputs for LVDS_25 can be placed in banks with V_CCO levels that are different from the required level for outputs. Consult the 7 Series FPGAs SelectIO Resources User Guide (UG471) [Ref 3] for more information.