Output Serializer/Deserializer Switching Characteristics

Setup/Hold

T_{OSDCK_D}/ T_{OSCKD_D}

D input setup/hold with respect to CLKDIV.

0.45/0.03

0.63/0.03

0.63/0.03

ns

T_{OSDCK_T}/ T_{OSCKD_T}

T input setup/hold with respect to CLK.

0.73/–0.13

0.88/–0.13

0.88/–0.13

ns

T_{OSDCK_T2}/ T_{OSCKD_T2}

T input setup/hold with respect to CLKDIV.

0.34/–0.13

0.39/–0.13

0.39/–0.13

ns

T_{OSCCK_OCE}/T_{OSCKC_OCE}

OCE input setup/hold with respect to CLK.

0.34/0.58

0.51/0.58

0.51/0.58

ns

T_{OSCCK_S}

SR (reset) input setup with respect to CLKDIV.

0.52

0.85

0.85

ns

T_{OSCCK_TCE}/T_{OSCKC_TCE}

TCE input setup/hold with respect to CLK.

0.34/0.01

0.51/0.01

0.51/0.01

ns

Sequential Delays

T_{OSCKO_OQ}

Clock to out from CLK to OQ.

0.42

0.48

0.48

ns

T_{OSCKO_TQ}

Clock to out from CLK to TQ.

0.49

0.56

0.56

ns

Combinatorial

T_{OSDO_TTQ}

T input to TQ out.

0.92

1.11

1.11

ns