Performance Characteristics

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS189)

Document ID

DS189

Release Date

2022-10-31

Revision

1.10 English

This section provides the performance characteristics of some common functions and designs implemented in Spartan-7 FPGAs. These values are subject to the same guidelines as the AC Switching Characteristics.

Table 15: Networking Applications Interface Performances
Description	V_CCINT Operating Voltage, Speed Grade, and Temperature Range			Units
	1.0V		0.95V
	-2C/-2I	-1C/-1I/-1Q	-1LI
SDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 8)	680	600	600	Mb/s
DDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 14)	1250	950	950	Mb/s
SDR LVDS receiver⁽¹⁾	680	600	600	Mb/s
DDR LVDS receiver⁽¹⁾	1250	950	950	Mb/s
Notes: 1.LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) algorithms dominate deterministic performance.

Table 16: Maximum Physical Interface (PHY) Rate for Memory Interface IP available with the Memory Interface Generator⁽¹⁾
Memory Standard	V_CCINT Operating Voltage, Speed Grade, and Temperature Range				Units
	1.0V			0.95V
	-2C/-2I	-1C/-1I	-1Q	-1LI
4:1 Memory Controllers
DDR3	800⁽²⁾	667	667	667	Mb/s
DDR3L	800⁽²⁾	667	667	667	Mb/s
DDR2	800⁽²⁾	667	533	667	Mb/s
2:1 Memory Controllers
DDR3	800⁽²⁾	667	667	667	Mb/s
DDR3L	800⁽²⁾	667	667	667	Mb/s
DDR2	800⁽²⁾	667	533	667	Mb/s
LPDDR2	667	533	400	533	Mb/s
Notes: 1.V_REF tracking is required. For more information, see the Zynq-7000 SoC and 7 Series Devices Memory Interface Solutions User Guide (UG586) [Ref 7]. 2.The maximum PHY rate is 667 Mb/s in the FTGB196 package.