Symbol |
Description |
VCCINT Operating Voltage and Speed Grade |
Units |
||
---|---|---|---|---|---|
1.0V |
0.95V |
||||
-2 |
-1 |
-1L |
|||
Setup and Hold Times of Data/Control Pins to the Input Register Clock |
|||||
TDSPDCK_A_AREG/ |
A input to A register CLK. |
0.30/0.13 |
0.37/0.14 |
0.37/0.14 |
ns |
TDSPDCK_B_BREG/ |
B input to B register CLK. |
0.38/0.16 |
0.45/0.18 |
0.45/0.18 |
ns |
TDSPDCK_C_CREG/ |
C input to C register CLK. |
0.20/0.19 |
0.24/0.21 |
0.24/0.21 |
ns |
TDSPDCK_D_DREG/ |
D input to D register CLK. |
0.32/0.27 |
0.42/0.27 |
0.42/0.27 |
ns |
TDSPDCK_ACIN_AREG/ TDSPCKD_ACIN_AREG |
ACIN input to A register CLK. |
0.27/0.13 |
0.32/0.14 |
0.32/0.14 |
ns |
TDSPDCK_BCIN_BREG/ TDSPCKD_BCIN_BREG |
BCIN input to B register CLK. |
0.29/0.16 |
0.36/0.18 |
0.36/0.18 |
ns |
Setup and Hold Times of Data Pins to the Pipeline Register Clock |
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TDSPDCK_{A, B}_MREG_MULT/ TDSPCKD_{A, B}_MREG_MULT |
{A, B} input to M register CLK using multiplier. |
2.76/–0.01 |
3.29/–0.01 |
3.29/–0.01 |
ns |
TDSPDCK_{A, D}_ADREG/ |
{A, D} input to AD register CLK. |
1.48/–0.02 |
1.76/–0.02 |
1.76/–0.02 |
ns |
Setup and Hold Times of Data/Control Pins to the Output Register Clock |
|||||
TDSPDCK_{A, B}_PREG_MULT/ TDSPCKD_{A, B} _PREG_MULT |
{A, B} input to P register CLK using multiplier. |
4.60/–0.28 |
5.48/–0.28 |
5.48/–0.28 |
ns |
TDSPDCK_D_PREG_MULT/ TDSPCKD_D_PREG_MULT |
D input to P register CLK using multiplier. |
4.50/–0.73 |
5.35/–0.73 |
5.35/–0.73 |
ns |
TDSPDCK_{A, B} _PREG/ |
A or B input to P register CLK not using multiplier. |
1.98/–0.28 |
2.35/–0.28 |
2.35/–0.28 |
ns |
TDSPDCK_C_PREG/ |
C input to P register CLK not using multiplier. |
1.76/–0.26 |
2.10/–0.26 |
2.10/–0.26 |
ns |
TDSPDCK_PCIN_PREG/ |
PCIN input to P register CLK. |
1.51/–0.15 |
1.80/–0.15 |
1.80/–0.15 |
ns |
Setup and Hold Times of the CE Pins |
|||||
TDSPDCK_{CEA;CEB}_{AREG;BREG}/ TDSPCKD_{CEA;CEB}_{AREG;BREG} |
{CEA; CEB} input to {A; B} register CLK. |
0.42/0.08 |
0.52/0.11 |
0.52/0.11 |
ns |
TDSPDCK_CEC_CREG/ TDSPCKD_CEC_CREG |
CEC input to C register CLK. |
0.34/0.11 |
0.42/0.13 |
0.42/0.13 |
ns |
TDSPDCK_CED_DREG/ TDSPCKD_CED_DREG |
CED input to D register CLK. |
0.43/–0.03 |
0.52/–0.03 |
0.52/–0.03 |
ns |
TDSPDCK_CEM_MREG/ TDSPCKD_CEM_MREG |
CEM input to M register CLK. |
0.21/0.20 |
0.27/0.23 |
0.27/0.23 |
ns |
TDSPDCK_CEP_PREG/ TDSPCKD_CEP_PREG |
CEP input to P register CLK. |
0.43/0.01 |
0.53/0.01 |
0.53/0.01 |
ns |
Setup and Hold Times of the RST Pins |
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TDSPDCK_{RSTA; RSTB}_{AREG; BREG}/ TDSPCKD_{RSTA; RSTB}_{AREG; BREG} |
{RSTA, RSTB} input to {A, B} register CLK. |
0.46/0.13 |
0.55/0.15 |
0.55/0.15 |
ns |
TDSPDCK_RSTC_CREG/ TDSPCKD_RSTC_CREG |
RSTC input to C register CLK. |
0.08/0.11 |
0.09/0.12 |
0.09/0.12 |
ns |
TDSPDCK_RSTD_DREG/ TDSPCKD_RSTD_DREG |
RSTD input to D register CLK |
0.50/0.08 |
0.59/0.09 |
0.59/0.09 |
ns |
TDSPDCK_RSTM_MREG/ TDSPCKD_RSTM_MREG |
RSTM input to M register CLK |
0.23/0.24 |
0.27/0.28 |
0.27/0.28 |
ns |
TDSPDCK_RSTP_PREG/ TDSPCKD_RSTP_PREG |
RSTP input to P register CLK |
0.30/0.01 |
0.35/0.01 |
0.35/0.01 |
ns |
Combinatorial Delays from Input Pins to Output Pins |
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TDSPDO_A_CARRYOUT_MULT |
A input to CARRYOUT output using multiplier. |
4.35 |
5.18 |
5.18 |
ns |
TDSPDO_D_P_MULT |
D input to P output using multiplier. |
4.26 |
5.07 |
5.07 |
ns |
TDSPDO_B_P |
B input to P output not using multiplier. |
1.75 |
2.08 |
2.08 |
ns |
TDSPDO_C_P |
C input to P output. |
1.53 |
1.82 |
1.82 |
ns |
Combinatorial Delays from Input Pins to Cascading Output Pins |
|||||
TDSPDO_{A; B}_{ACOUT; BCOUT} |
{A, B} input to {ACOUT, BCOUT} output. |
0.63 |
0.74 |
0.74 |
ns |
TDSPDO_{A, B}_CARRYCASCOUT_MULT |
{A, B} input to CARRYCASCOUT output using multiplier. |
4.65 |
5.54 |
5.54 |
ns |
TDSPDO_D_CARRYCASCOUT_MULT |
D input to CARRYCASCOUT output using multiplier. |
4.54 |
5.40 |
5.40 |
ns |
TDSPDO_{A, B}_CARRYCASCOUT |
{A, B} input to CARRYCASCOUT output not using multiplier. |
2.03 |
2.41 |
2.41 |
ns |
TDSPDO_C_CARRYCASCOUT |
C input to CARRYCASCOUT output. |
1.81 |
2.15 |
2.15 |
ns |
Combinatorial Delays from Cascading Input Pins to All Output Pins |
|||||
TDSPDO_ACIN_P_MULT |
ACIN input to P output using multiplier. |
4.19 |
5.00 |
5.00 |
ns |
TDSPDO_ACIN_P |
ACIN input to P output not using multiplier. |
1.57 |
1.88 |
1.88 |
ns |
TDSPDO_ACIN_ACOUT |
ACIN input to ACOUT output. |
0.44 |
0.53 |
0.53 |
ns |
TDSPDO_ACIN_CARRYCASCOUT_MULT |
ACIN input to CARRYCASCOUT output using multiplier. |
4.47 |
5.33 |
5.33 |
ns |
TDSPDO_ACIN_CARRYCASCOUT |
ACIN input to CARRYCASCOUT output not using multiplier. |
1.85 |
2.21 |
2.21 |
ns |
TDSPDO_PCIN_P |
PCIN input to P output. |
1.28 |
1.52 |
1.52 |
ns |
TDSPDO_PCIN_CARRYCASCOUT |
PCIN input to CARRYCASCOUT output. |
1.56 |
1.85 |
1.85 |
ns |
Clock to Outs from Output Register Clock to Output Pins |
|||||
TDSPCKO_P_PREG |
CLK PREG to P output. |
0.37 |
0.44 |
0.44 |
ns |
TDSPCKO_CARRYCASCOUT_PREG |
CLK PREG to CARRYCASCOUT output. |
0.59 |
0.69 |
0.69 |
ns |
Clock to Outs from Pipeline Register Clock to Output Pins |
|||||
TDSPCKO_P_MREG |
CLK MREG to P output. |
1.93 |
2.31 |
2.31 |
ns |
TDSPCKO_CARRYCASCOUT_MREG |
CLK MREG to CARRYCASCOUT output. |
2.21 |
2.64 |
2.64 |
ns |
TDSPCKO_P_ADREG_MULT |
CLK ADREG to P output using multiplier. |
3.10 |
3.69 |
3.69 |
ns |
TDSPCKO_CARRYCASCOUT_ADREG_MULT |
CLK ADREG to CARRYCASCOUT output using multiplier. |
3.38 |
4.02 |
4.02 |
ns |
Clock to Outs from Input Register Clock to Output Pins |
|||||
TDSPCKO_P_AREG_MULT |
CLK AREG to P output using multiplier. |
4.51 |
5.37 |
5.37 |
ns |
TDSPCKO_P_BREG |
CLK BREG to P output not using multiplier. |
1.87 |
2.22 |
2.22 |
ns |
TDSPCKO_P_CREG |
CLK CREG to P output not using multiplier. |
1.93 |
2.30 |
2.30 |
ns |
TDSPCKO_P_DREG_MULT |
CLK DREG to P output using multiplier. |
4.48 |
5.32 |
5.32 |
ns |
Clock to Outs from Input Register Clock to Cascading Output Pins |
|||||
TDSPCKO_{ACOUT; BCOUT}_ |
CLK (ACOUT, BCOUT) to {A,B} register output. |
0.73 |
0.87 |
0.87 |
ns |
TDSPCKO_CARRYCASCOUT_ |
CLK (AREG, BREG) to CARRYCASCOUT output using multiplier. |
4.79 |
5.70 |
5.70 |
ns |
TDSPCKO_CARRYCASCOUT_ BREG |
CLK BREG to CARRYCASCOUT output not using multiplier. |
2.15 |
2.55 |
2.55 |
ns |
TDSPCKO_CARRYCASCOUT_ DREG_MULT |
CLK DREG to CARRYCASCOUT output using multiplier. |
4.76 |
5.65 |
5.65 |
ns |
TDSPCKO_CARRYCASCOUT_ CREG |
CLK CREG to CARRYCASCOUT output. |
2.21 |
2.63 |
2.63 |
ns |
Maximum Frequency |
|||||
FMAX |
With all registers used. |
550.66 |
464.25 |
464.25 |
MHz |
FMAX_PATDET |
With pattern detector. |
465.77 |
392.93 |
392.93 |
MHz |
FMAX_MULT_NOMREG |
Two register multiply without MREG. |
305.62 |
257.47 |
257.47 |
MHz |
FMAX_MULT_NOMREG_PATDET |
Two register multiply without MREG with pattern detect. |
277.62 |
233.92 |
233.92 |
MHz |
FMAX_PREADD_MULT_NOADREG |
Without ADREG. |
346.26 |
290.44 |
290.44 |
MHz |
FMAX_PREADD_MULT_NOADREG_PATDET |
Without ADREG with pattern detect. |
346.26 |
290.44 |
290.44 |
MHz |
FMAX_NOPIPELINEREG |
Without pipeline registers (MREG, ADREG). |
227.01 |
190.69 |
190.69 |
MHz |
FMAX_NOPIPELINEREG_PATDET |
Without pipeline registers (MREG, ADREG) with pattern detect. |
211.15 |
177.43 |
177.43 |
MHz |