Device Pin-to-Pin Input Parameter Guidelines

Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.⁽¹⁾

T_PSFD/ T_PHFD

Full delay (legacy delay or default delay) global clock input and IFF⁽²⁾ without MMCM/PLL with ZHOLD_DELAY on HR I/O banks.

XC7S6

2.76/–0.40

3.17/–0.40

3.17/–0.40

ns

XC7S15

2.76/–0.40

3.17/–0.40

3.17/–0.40

ns

XC7S25

2.67/–0.37

3.12/–0.37

3.12/–0.37

ns

XC7S50

2.66/–0.28

3.11/–0.28

3.11/–0.28

ns

XC7S75

2.91/–0.33

3.36/–0.33

3.36/–0.33

ns

XC7S100

2.91/–0.33

3.36/–0.33

3.36/–0.33

ns

XA7S6

2.76/–0.40

3.17/–0.40

N/A

ns

XA7S15

2.76/–0.40

3.17/–0.40

N/A

ns

XA7S25

2.67/–0.37

3.12/–0.37

N/A

ns

XA7S50

2.66/–0.28

3.11/–0.28

N/A

ns

XA7S75

2.91/–0.33

3.36/–0.33

N/A

ns

XA7S100

2.91/–0.33

3.36/–0.33

N/A

ns

Notes:

1.Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage.

2.IFF = Input flip-flop or latch.

Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.⁽¹⁾⁽²⁾

T_PSMMCMCC/ T_PHMMCMCC

No delay clock-capable clock input and IFF⁽³⁾ with MMCM.

XC7S6

2.73/–0.59

3.27/–0.59

3.27/–0.59

ns

XC7S15

2.73/–0.59

3.27/–0.59

3.27/–0.59

ns

XC7S25

2.69/–0.61

3.21/–0.61

3.21/–0.61

ns

XC7S50

2.81/–0.62

3.35/–0.62

3.35/–0.62

ns

XC7S75

2.81/–0.62

3.36/–0.62

3.36/–0.62

ns

XC7S100

2.81/–0.62

3.36/–0.62

3.36/–0.62

ns

XA7S6

2.73/–0.59

3.27/–0.59

N/A

ns

XA7S15

2.73/–0.59

3.27/–0.59

N/A

ns

XA7S25

2.69/–0.61

3.21/–0.61

N/A

ns

XA7S50

2.81/–0.62

3.35/–0.62

N/A

ns

XA7S75

2.81/–0.62

3.36/–0.62

N/A

ns

XA7S100

2.81/–0.62

3.36/–0.62

N/A

ns

Notes:

1.Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage.

2.Use IBIS to determine any duty-cycle distortion incurred using various standards.

3.IFF = Input flip-flop or latch.

Input Setup and Hold Time Relative to Clock-Capable Clock Input Signal for SSTL15 Standard.⁽¹⁾⁽²⁾

T_PSPLLCC/ T_PHPLLCC

No delay clock-capable clock input and IFF⁽³⁾ with PLL.

XC7S6

3.07/–0.17

3.69/–0.17

3.69/–0.17

ns

XC7S15

3.07/–0.17

3.69/–0.17

3.69/–0.17

ns

XC7S25

3.04/–0.19

3.64/–0.19

3.64/–0.19

ns

XC7S50

3.15/–0.19

3.77/–0.19

3.77/–0.19

ns

XC7S75

3.15/–0.19

3.78/–0.19

3.78/–0.19

ns

XC7S100

3.15/–0.19

3.78/–0.19

3.78/–0.19

ns

XA7S6

3.07/–0.17

3.69/–0.17

N/A

ns

XA7S15

3.07/–0.17

3.69/–0.17

N/A

ns

XA7S25

3.04/–0.19

3.64/–0.19

N/A

ns

XA7S50

3.15/–0.19

3.77/–0.19

N/A

ns

XA7S75

3.15/–0.19

3.78/–0.19

N/A

ns

XA7S100

3.15/–0.19

3.78/–0.19

N/A

ns

Notes:

1.Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage.

2.Use IBIS to determine any duty-cycle distortion incurred using various standards.

3.IFF = Input flip-flop or latch.

Input Setup and Hold Time Relative to a Forwarded Clock Input Pin Using BUFIO for SSTL15 Standard.

T_PSCS/T_PHCS

Setup and hold of I/O clock.

–0.38/1.46

–0.38/1.73

–0.38/1.76

ns

T_SAMP

Sampling error at receiver pins.⁽¹⁾

0.64

0.70

0.70

ns

T_{SAMP_BUFIO}

Sampling error at receiver pins using BUFIO.⁽²⁾

0.40

0.46

0.46

ns

Notes:

1.This parameter indicates the total sampling error of the Spartan-7 FPGAs DDR input registers, measured across voltage, temperature, and process. The characterization methodology uses the MMCM to capture the DDR input registers’ edges of operation. These measurements include:

- CLK0 MMCM jitter

- MMCM accuracy (phase offset)

- MMCM phase shift resolution

These measurements do not include package or clock tree skew.

2.This parameter indicates the total sampling error of the Spartan-7 FPGAs DDR input registers, measured across voltage, temperature, and process. The characterization methodology uses the BUFIO clock network and IDELAY to capture the DDR input registers’ edges of operation. These measurements do not include package or clock tree skew.