DSP58 has the ability to perform a 116-bit wide XOR function. The XOR uses the X, Y, and Z multiplexers as inputs. The W multiplexer selects all 0s at its output. The ALU logic is used for the first stage of the wide XOR by using the proper OPMODE and ALUMODE signals as shown in Table 1, to implement either X XOR Z, or X XOR Y XOR Z. The signals then branch out to an XOR logic tree with dedicated outputs. Multiplexers allow selection as six 12-bit and two 22-bit wide XOR, two 24-bit and two 34-bit wide XOR, two 58-bit wide XOR, or one 116-bit wide XOR (see the following figure). In the following figure, the S[57:0] internal bus is not the P[57:0] output, it is one of the 4:2 compressor buses.
The XORSIMD attribute is used to select the width of the XOR function as either 116-bit or 12/22/24/34/58 bits, as shown in the following table.
| XORSIMD Attribute | XOR Width | XOR INPUT Bits (A:B^C) | Corresponding XOROUT |
|---|---|---|---|
| XOR12_22 |
6 × 12-bit 2 × 22-bit |
S[5:0] | XOROUT[0] |
| S[11:6] | XOROUT[1] | ||
| S[17:12] | XOROUT[2] | ||
| S[52:48, 23:18] | XOROUT[3] | ||
| S[29:24] | XOROUT[4] | ||
| S[35:30] | XOROUT[5] | ||
| S[41:36] | XOROUT[6] | ||
| S[57:53, 47:42] | XOROUT[7] | ||
| XOR24_34_58_116 |
2 × 24-bit 2 × 34-bit |
S[11:0] | XOROUT[0] |
| S[52:48, 23:12] | XOROUT[2] | ||
| S[35:24] | XOROUT[4] | ||
| S[57:53, 47:36] | XOROUT[6] | ||
| 2 × 58-bit | S[52:48, 23:0] | XOROUT[1] | |
| S[57:53, 47:24] | XOROUT[5] | ||
| 1 × 116-bit | S[57:0] | XOROUT[3] |
The first level XOR can either be XOR2 or XOR3. In both cases, ALUMODE[3:0] =
0100 for the XOR function in the ALU. When the Y multiplexer
selects 0, an XOR2 is created. When the Y multiplexer selects the C
register, an XOR3 is created, supporting up to 58 XOR3 in the ALU. The third input
can come from the P output or the PCIN cascade, which provides XOR-accumulate and
cascade capability for even wider XOR functions.