Design Entry

Versal ACAP DSP Engine Architecture Manual (AM004)

Document ID
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1.2.1 English

Xilinx offers integrated DSP design flows tailored for the unique needs of hardware, algorithm, and traditional processor-based DSP designers, supporting all mainstream DSP design entry methods to ensure productivity. Vivado® Design Suite includes an extensive library of device-optimized DSP IP to quickly assemble DSP designs that deliver high-quality results without requiring extensive programmable logic design experience. DSP algorithms implemented in RTL can be verified from within DSP specific simulation environments such as MATLAB® / Simulink® or C/C++. The DSP58s are inferred automatically from HDL code for most DSP functions and many arithmetic functions when using synthesis tools. Instantiation of the DSP58 primitive can be used to directly access specific features and provide more advanced user control.

Table 1. Design Entry Methods
Method Support
Instantiation Yes
Inference Recommended
Vivado Design Suite IP catalog Yes
Macros Yes

DSP58 is a strict superset of the DSP48E2. When re-targeting from the UltraScale™ architecture, instantiation of the DSP48E2 is translated appropriately to the Versal architecture using the DSP48E5 internal primitive which is used by simulation and appears in a netlist. Code for inferring the following examples is provided by Xilinx.

  • Fully pipelined 16 × 16 multiplier
  • Fully pipelined 27 × 24 multiplier
  • Multiply add
  • 16-bit adder
  • 16-bit adder, the same value on both inputs to the adder
  • Loadable multiply
  • Complex 18 × 18 multiplier mapping to one DSPCPLX unit
  • 3 × dot product of 9-bit and 8-bit two's complement fixed point numbers
Note: Inference for DSPFP32 (single and half precision) is not supported. It can be instantiated and it is recommended that customers use the Floating Point Operator IP core in the Vivado IP catalog to implement the function.