27 × 24 Complex Multiply

Versal ACAP DSP Engine Architecture Manual (AM004)

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1.2.1 English

The three DSP58s version in the legacy mode can handle up to 26 × 23 complex multiply. For full bit width 27 × 24, four DSP58s are required. Two DSP58s implement the real part and the other two implement the imaginary part. Up until 26 × 23, the three DSP58s version is preferable because it uses one DSP less. However, note that the performance could lower while the power increases because the design has to pass through programmable interconnect. The implementation with four DSPs uses the dedicated cascade path in the DSP logic and is the better choice for performance and power dissipation. See the following block diagrams for the implementation of real and imaginary parts.

The implementation refers to the following case.

Figure 1. Real Part of a 27 × 24 Bits Complex Multiplier
Figure 2. Imaginary Part of a 27 × 24 Bits Complex Multiplier