Floating Point FIR Filter

Versal ACAP DSP Engine Architecture Manual (AM004)

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1.2.1 English

The design in this use case essentially implements the single multiplier MACC FIR filter in a floating point data format. Refer to the figure in Resource Utilization Guideline for a simplified block diagram of the design. Note the following:

  • The DSPFP32 replaces the DSP58 primitive and consists of a floating-point multiplier and a floating-point adder.
  • The input and output are in IEEE binary32 format.
  • The single-port block RAM is partitioned into two: one half is dedicated to the incoming data, the other half is used as ROM for the coefficients.
  • FPOPMODE[6:0] controls the behavior of the floating-point arithmetic unit and is configured to be {00c0001}. The OPMODE bit ‘c’ is sent to the DSP from the control logic and dynamically selects the input to the ALU to enable or disable the P output feedback path. This is done to reset the accumulator from one output sequence to another. This approach means avoiding a reset to the output register, saving a clock cycle.

The reference design files associated with this use case are available in the floating_point_FIR directory in the design archive file, am004-versal-dsp-engine.zip.