Versal ACAP DSP Engine Architecture Manual (AM004)

Document ID
Release Date
1.2.1 English

DSP58 has a 27-bit pre-adder, which is inserted in the A or B register path (shown in Figure 1 with an expanded view in Figure 1). With the pre-adder, pre-additions or pre-subtractions are possible prior to feeding the multiplier. The pre-adder does not contain saturation logic and thus, the designers must limit input operands to 26-bit (or 23-bit for the B path) two’s complement sign-extended data to avoid overflow or underflow during arithmetic operations. Optionally, the pre-adder can be bypassed, making D the new input path to the multiplier. When the D path is not used, the output of the A or B pipeline can be negated prior to driving the multiplier. There are up to 15 operating modes, including pre-adder squaring, making this pre-adder block very flexible.

In the following equations, A (or B) and D are added initially through the pre-adder/subtracter. The result of the pre-adder is then multiplied against B (or A), with the result of the multiplication being added to the C input. The following equations facilitate efficient symmetric filters.