Device Resources

Versal ACAP DSP Engine Architecture Manual (AM004)

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1.2.1 English

The DSP resources are optimized and scalable across the Versal® portfolio, providing a common architecture that improves implementation efficiency, IP implementation, and design migration. Migration within the Versal portfolio does not require any design changes to DSP58. When migrating from the UltraScale™ architecture to Versal architecture, because DSP58 is a superset of DSP48E2, an instantiation of the DSP48E2 is translated to DSP58.

The DSP super tiles stack vertically to form a DSP super column. The height of a DSP super tile is the same as two configurable logic blocks (CLBs). It matches both the height of one 18K block RAM and half a 288K UltraRAM. Two 18K block RAMs stack vertically to form a 36K block RAM (see the following figure).

Figure 1. DSP Super Columns and RAM Resources

The Versal adaptive compute acceleration platform (ACAPs) DSP column has 48 DSP58s per clock region. There are 96 DSP58s per column per clock region because with the Versal architecture, the DSP58s always come in back-to-back pairs. DSP58s can be cascaded across clock regions up to the boundary of the device, or of a super logic region (SLR) in 3D ICs based on SSI technology. The number of cascadeable DSPs in a column can be found using the following Tcl command:

expr {[llength [get_sites DSP_X0* -of_objects [get_slrs SLR0]]]}

The following table shows the maximum number of DSP58s that can be directly cascaded vertically in a column, and the total number of DSP58s for the Versal ACAPs.

Table 1. Maximum Number of Cascadable DSP58s in Versal ACAPs
Device name Max Cascade Number of DSP58s
VM1102 116 464
VM1302 212 848
VM1402 212 1,696
VM1502 164 1,312
VM1802 164 1,968
VM2202 164 1,312
VM2302 334 1,904
VM2502 166 3,984
VM2902 334 2,672
VC1352 116 928
VC1502 164 1,032
VC1702 164 1,312
VC1802 164 1,600
VC1902 164 1,968
VC2602 164 984
VC2802 164 1,312