Adder Cascade

Versal ACAP DSP Engine Architecture Manual (AM004)

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1.2.1 English

The adder cascade implementation accomplishes the post addition process with minimal silicon resources by using the cascade path within the DSP58. This involves computing the additive result incrementally, using a cascaded approach as illustrated in the following figure.

Figure 1. Adder Cascade

It is important to balance the delay of the input sample and the coefficients in the cascaded adder to achieve correct results. The coefficients are staggered in time.