Three Multiplier Semi-Parallel FIR Filter

Versal ACAP DSP Engine Architecture Manual (AM004)

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1.2.1 English

For the semi-parallel FIR case with moderate to high sample rate and large number of coefficients, the filter structure is chosen to be the three-multiplier, block RAM based, semi-parallel FIR filter. The following figure is a block diagram of the filter.

Figure 1. Three-Multiplier, Block RAM Based, Semi-Parallel FIR Filter

In this implementation, one memory buffer is required to hold the coefficients and also the input data history values. The block RAM can be used in dual-port mode with a cyclic data buffer established in the first half of the memory to serve the shifting input data series. There are 16 taps for each DSP and the overall number of taps in this design is 48.

The reference design files for this use case are available in the semi_parallel_FIR directory in the design archive file,