Recommended Design Flow

Versal ACAP DSP Engine Architecture Manual (AM004)

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1.2.1 English

Many DSP58 designs are well suited for Versal® ACAPs. To obtain best use of the architecture, underlying features, and capabilities must be understood so that the design entry code can take advantage of these resources. DSP resources are used automatically for most DSP functions and many arithmetic functions. In most cases, DSP resources must be inferred. See your preferred synthesis tool documentation for guidelines to ensure proper inference of the DSP. Instantiation of the DSP primitive can be used to directly access specific features. Recommendations for using DSP58 include:

  • Use signed values in HDL source
  • Pipeline for performance and lower power in DSP58 and programmable logic (PL)
  • Use configurable logic block (CLB) shift register LUTs (SRLs), CLB distributed RAM, and/or block RAM to store filter coefficients
  • Set USE_MULT to NONE when using only the adder/logic unit to save power
  • Cascade using the dedicated resources rather than general-purpose interconnect, keeping usage to one column for highest performance and lowest power
  • Consider using time multiplexing if resources are limited in a lower-speed application
  • Use the CLB carry logic to implement small multipliers, adders, and counters

For more information on design techniques, see DSP58 Design Considerations.