Decimating is the process of reducing the number of samples representing a signal. Decimation is used in video applications like 4:4:4-to-4:2:2 conversions and HDTV-to-SDTV conversions. The following figure illustrates a 16-tap 4:1 decimator implemented using four parallel filters. The phases are related to the number of DSP58s and the number of coefficients is related to the memory depth (if RAM is used) or number of registers (SRL16). For every four-input sample, the decimator produces one output sample.

For the 16-tap filter, the output sample (y) is the weighted average of 16 input samples (x) multiplied by 16 coefficients (h) as described in the following equation.

_{[n]}= (h

_{0}× x

_{n}) + (h

_{1}× x

_{n – 1}) + (h

_{2}× x

_{n – 2}) + (h

_{3}× x

_{n – 3}) + (h

_{4}× x

_{n – 4}) + (h

_{5}× x

_{n – 5}) + (h

_{6}× x

_{n – 6}) + (h

_{7}× x

_{n – 7}) + (h

_{8}× x

_{n – 8}) + (h

_{9}× x

_{n – 9}) + (h

_{10}× x

_{n – 10}) + (h

_{11}× x

_{n – 11}) + (h

_{12}× x

_{n – 12}) + (h

_{13}× x

_{n – 13}) + (h

_{14}× x

_{n – 14}) + (h

_{15}× x

_{n – 15})

The input signals to each DSP58 are delayed by (M + 1) clocks from the previous DSP58. Shift registers are used to achieve this delay. An initial latency is given by the following equation.

The 16-tap filter output is obtained at the fourth DSP58. The OPMODE must be changed dynamically to ensure functionality.

The reference design files associated with this use case are available in the multirate_FIR/polyphase_decimating_FIR directory in the design archive file, am004-versal-dsp-engine.zip.