Pattern Detect Logic

Versal ACAP DSP Engine Architecture Manual (AM004)

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1.2.1 English

The pattern detector is connected to the output of the add/subtract/logic unit in DSP58. The pattern detector is best described as an equality check on the output of the adder/subtracter/logic unit that produces its result on the same cycle as the P output. There is no extra latency between the pattern detect output and the P output of DSP58. The use of the pattern detector leads to a moderate speed reduction due to the extra logic on the pattern detect path (see the following figure).

Figure 1. Pattern Detector Logic

Some of the applications that can be implemented using the pattern detector are:

  • Pattern detect with optional mask
  • Dynamic C input pattern match with A x B
  • Overflow/underflow/saturation past P[56] (or P[46] when DSP_MODE = DSP48E2)
  • A:B = = C and dynamic pattern match, for example, A:B OR C = = 0, A:B AND C == 1
  • A:B {function} C = = 0
  • 58-bit (48-bit for DSP_MODE = DSP48E2) counter auto reset (terminal count detection) with option for CEP priority
  • Detecting mid points for rounding operations

If the pattern detector is not being employed, it can be used for other creative design implementations. These include:

  • Duplicating a pin (for example, the sign bit) to reduce fanout and thus increase speed.
  • Implementing a built-in inverter on one bit (for example, the sign bit) without having to route out to the CLBs.
  • Checking for sticky bits in floating-point, handling special cases, or monitoring DSP58 outputs.
  • Raising a flag if a certain condition is met or if a certain condition is no longer met.

A mask field can also be used to mask out certain bit locations in the pattern detector. The pattern field and the mask field can each come from a distinct 58-bit memory cell field or from the (registered) C input.

Note: For the mask field, all 1's are not valid because it would make PATTERNDETECT always equal to 1.