DSPFP32 Unisim Primitive

Versal ACAP DSP Engine Architecture Manual (AM004)

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1.2.1 English

The DSPFP32 consists of a floating point multiplier and a floating point adder with separate outputs in the binary 32 format going into the internal logic. Each floating point multiplier input can be in either the IEEE binary32 (FP32 or single-precision) or binary16 (FP16 or half-precision) format, whereas the floating point adder only accepts binary32 inputs. Outputs are always in FP32 or single precision format. The adder has an internal loop-back path to form an accumulator in a single cycle. The multiplier output can also feed the adder internally without logic routing to form a multiply-add (MADD) or multiply-accumulate (MACC) unit. Alternatively, the P output of the FP adder (FPA) can feedback to a MUX with the C input with FPCREG = 3 to form an accumulator chain supporting up to four threads of MACC computation.

The two outputs of the floating point unit are M = A × M0 and P = ±P0 ±P1, see the following figure. Both M and P are rounded and only the IEEE round-to-nearest-even mode is supported.

Note: M0 is an internal node that can receive input from either input B or port D controlled by FPINMODE because of the ping-pong input feature.
Figure 1. Floating Point Multiplier and Adder (DSPFP32 Mode)