Revision History

Versal ACAP DSP Engine Architecture Manual (AM004)

Document ID
Release Date
1.2.1 English

The following table shows the revision history for this document.

Section Revision Summary
09/11/2022 Version 1.2.1
General updates Corrected publication date.
09/08/2022 Version 1.2
Complex Multiplier

Expanded OPMODE Control description, adding definitions for the X,Y,Z,W multiplexers input/output relationships and descriptions of complex multiplication operations with equations.

Added ALUMODE Control section describing control of operations performed by the final ALU.

MACC Extension New section added describing MACC operations.
12/23/2020 Version 1.1.1
General updates Editorial updates only. No technical content changes.
12/04/2020 Version 1.1
Figure 1 Updated to fix a connection on MUX from the output of the B2 register.
Bus Multiplexer Updated figure to add flop stages. Revised the table to update OPMODE settings.
Division Updated the dividing with multiplication case to change initial value Q[8-n] from B to A input.
Square Root Updated description to add the value for C.
Clock Domain Crossing and Time Division Multiplexing Updated description.
DSPCPLX Updated information related to Language Templates.
Figure 1 Updated figure to add a flop stage in PL as well as in DSP2.
Figure 2 Updated to share data_dp0 between the two DSP58s at the bottom, as well as add a flop after pre-adder in the two DSP58s at the bottom. Also, staged FPINMODE.
Resource Utilization Guideline Updated LUTRAM to SRL16/LUTRAM in the description. Updated figure to add signal RE from control to the coefficients block.
Single Multiplier MACC FIR Filter Updated implementation description.
Symmetric MACC FIR Filter Updated the FIR filter equation. Updated figure to add flop stages to A/B/D inputs of DSP58, as well as updated the input and output data width.
Three Multiplier Semi-Parallel FIR Filter Updated description to add number of taps. Updated figure to add flop stages to inputs A and B for all the DSP58s and added WE3 in control logic to control the output flop.
Systolic FIR Filter Added a note about swapping the A and B inputs in the systolic multiply-add processing element. Updated figure to add a note about C.
Symmetric Systolic FIR Filter Updated equation.
Interpolating Updated number of taps to 12. Updated figure to add a flop stage to input B.
Figure 1 Updated to add a flop stage to inputs A and B.
Decimating Updated figure to add a flop stage to input B. Updated the equation for initial latency.
Floating Point FIR Filter Updated description to add information about C in OPMODE.
Complex FIR Filter Updated equations.
07/16/2020 Version 1.0
Initial release. N/A