Benchmarks and Requirements

Versal ACAP DSP Engine Architecture Manual (AM004)

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1.2.1 English

A wide variety of filter architectures are available to design engineers. The type of architecture chosen is typically determined by the amount of processing required in the available number of clock cycles. The two most important factors are:

  • Sample rate (Fs)
  • Number of coefficients (N)

On one end, there are sequential processing FIR filters, including the single-multiplier MACC FIR filter, that usually offer the best solution when the sample rate is low. The MACC structure uses a single multiplier with an accumulator to implement an FIR filter sequentially. At the other end, as the sample rate increases, the architecture selected for a desired FIR filter becomes a more parallel structure (that is, semi-parallel and parallel FIR filters) involving more multiply and add elements. Between a single multiplier MACC FIR filter and a fully parallel full FIR filter, the trade-off with the MACC FIR filter is that not only does it reduce hardware by a factor of N but it also reduces filter throughput by the same factor.