Bus Multiplexer

Versal ACAP DSP Engine Architecture Manual (AM004)

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1.2.1 English

Wide bus multiplexers are used in many network switching applications where voice and data need to be multiplexed. In digital signal processing, a multiplexer is used to take several separate data streams and combine them into one single data stream at a higher rate. The DSP58 can be used to implement high-width (up to 58 bits) multiplexers for networking and video applications.

The OPMODE bits are used to choose between the C input and the A:B input within DSP58. Each DSP58 can multiplex between two 58-bit values. The following figure shows the implementation of a 58-bit-wide 8:1 multiplexer. Additional pipeline registers will be used to increase performance of the multiplexer.

Figure 1. 58-Bit-Wide 8:1 Multiplexer Using DSP58

The ALUMODE is set to 0000. Different OPMODE settings can be used for each of the four DSP58s. The following table lists one way of setting the OPMODEs to implement the 58-bit multiplexer. To drive the OPMODE setting to each DSP, PL logic is used. To optimize the speed of this multiplexer design, pipeline registers are added. The latency of the design is equal to number of (DSPs+1), which in this case is 5 clock cycles.

Table 1. OPMODE Settings for an 8:1 Multiplexer
OPMODE Selected Input
DSP58_3 DSP58_2 DSP58_1 DSP58_0
000010000 000010000 000010000 000000011 in 0
000010000 000010000 000010000 000001100 in 1
000010000 000010000 000000011 000000000 in 2
000010000 000010000 000001100 000000000 in 3
000010000 000000011 000000000 000000000 in 4
000010000 000001100 000000000 000000000 in 5
000000011 000000000 000000000 000000000 in 6
000001100 000000000 000000000 000000000 in 7

The reference design files associated with this use case are available in the multiplexer directory in the design archive file, am004-versal-dsp-engine.zip.